Patchwork [v5,5/6] powerpc: add Split Little Endian bit to MSR

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Submitter Cédric Le Goater
Date Nov. 5, 2013, 5:22 p.m.
Message ID <1383672128-26795-6-git-send-email-clg@fr.ibm.com>
Download mbox | patch
Permalink /patch/288594/
State New
Headers show

Comments

Cédric Le Goater - Nov. 5, 2013, 5:22 p.m.
Architecture 2.07 defines a new MSR Split Little Endian (SLE) bit,
which changes the order used for data storage accesses.

If MSR[SLE] is 0, instruction and data storage accesses for the
thread are the same and use the value specified by MSR[LE].

If MSR[SLE] is 1, instruction and data storage accesses for the
thread are opposite. Instruction storage accesses use the value
specified by MSR[LE]. Data storage accesses use the value specified
by ~MSR[LE].

The table below illustrates the Endian modes for all combinations
of MSR[SLE] and MSR[LE].

	SLE	LE	Data	Instruction

	0	0	Big	Big
	0	1	Little	Little
	1	0	Little	Big
	1	1	Big	Little

Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

This is clearly a powerpc patch but the following patch is for
kvm-ppc and it depends on it. I am not sure how to handle the
patch serie. Should I send to linuxppc-dev@lists.ozlabs.org also ? 

Thanks,

C.

 arch/powerpc/include/asm/reg.h |    3 +++
 arch/powerpc/kernel/process.c  |    1 +
 2 files changed, 4 insertions(+)

Patch

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 5c45787..1464ef9 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -29,6 +29,7 @@ 
 #define MSR_SF_LG	63              /* Enable 64 bit mode */
 #define MSR_ISF_LG	61              /* Interrupt 64b mode valid on 630 */
 #define MSR_HV_LG 	60              /* Hypervisor state */
+#define MSR_SLE_LG	58		/* Split Little Endian */
 #define MSR_TS_T_LG	34		/* Trans Mem state: Transactional */
 #define MSR_TS_S_LG	33		/* Trans Mem state: Suspended */
 #define MSR_TS_LG	33		/* Trans Mem state (2 bits) */
@@ -68,11 +69,13 @@ 
 #define MSR_SF		__MASK(MSR_SF_LG)	/* Enable 64 bit mode */
 #define MSR_ISF		__MASK(MSR_ISF_LG)	/* Interrupt 64b mode valid on 630 */
 #define MSR_HV 		__MASK(MSR_HV_LG)	/* Hypervisor state */
+#define MSR_SLE		__MASK(MSR_SLE_LG)	/* Split Little Endian */
 #else
 /* so tests for these bits fail on 32-bit */
 #define MSR_SF		0
 #define MSR_ISF		0
 #define MSR_HV		0
+#define MSR_SLE		0
 #endif
 
 #define MSR_VEC		__MASK(MSR_VEC_LG)	/* Enable AltiVec */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 5c466aa..7f87981 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -799,6 +799,7 @@  static struct regbit {
 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
 	{MSR_SF,	"SF"},
 	{MSR_HV,	"HV"},
+	{MSR_SLE,	"SLE"},
 #endif
 	{MSR_VEC,	"VEC"},
 	{MSR_VSX,	"VSX"},