From patchwork Tue Jun 16 20:23:32 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Paulraj X-Patchwork-Id: 28744 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by bilbo.ozlabs.org (Postfix) with ESMTPS id AC04BB71D2 for ; Wed, 17 Jun 2009 06:26:06 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.69 #1 (Red Hat Linux)) id 1MGfCY-0002FW-1n; Tue, 16 Jun 2009 20:24:14 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by bombadil.infradead.org with esmtps (Exim 4.69 #1 (Red Hat Linux)) id 1MGfCP-0001yq-Hy for linux-mtd@lists.infradead.org; Tue, 16 Jun 2009 20:24:12 +0000 Received: from dlep35.itg.ti.com ([157.170.170.118]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id n5GKNY2t004848; Tue, 16 Jun 2009 15:23:39 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id n5GKNXPP014055; Tue, 16 Jun 2009 15:23:33 -0500 (CDT) Received: from gt5d9d821.telogy.design.ti.com (gt5d9d821.telogy.design.ti.com [158.218.100.23]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id n5GKNX902012; Tue, 16 Jun 2009 15:23:33 -0500 (CDT) Received: from gt5d9d821.telogy.design.ti.com (localhost.localdomain [127.0.0.1]) by gt5d9d821.telogy.design.ti.com (8.13.1/8.13.1) with ESMTP id n5GKNWA4011526; Tue, 16 Jun 2009 16:23:32 -0400 Received: (from a0866907@localhost) by gt5d9d821.telogy.design.ti.com (8.13.1/8.13.1/Submit) id n5GKNWum011523; Tue, 16 Jun 2009 16:23:32 -0400 From: s-paulraj@ti.com To: davinci-linux-open-source@linux.davincidsp.com, linux-mtd@lists.infradead.org, dwmw2@infradead.org, tglx@linutronix.de, akpm@linux-foundation.org Subject: [PATCH v2 3/3] Add 4-bit ECC support for large page NAND chips on Davinci Date: Tue, 16 Jun 2009 16:23:32 -0400 Message-Id: <1245183812-11500-1-git-send-email-s-paulraj@ti.com> X-Mailer: git-send-email 1.6.0.4 X-Spam-Score: 0.0 (/) Cc: Sneha Narnakaje , Sandeep Paulraj X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Sandeep Paulraj The patch applies to linux-mtd GIT tree This patch adds 4-bit ECC support for large page NAND chips using the new ECC mode NAND_ECC_HW_OOB_FIRST. The platform data from board-dm355-evm has been adjusted to use this mode. The patches have been verified on DM355 device with 2K and 4K page size Micron devices using mtd-tests. Error correction upto 4-bits has also been verified using nandwrite/nanddump utilities. Reviewed-by: David Brownell Signed-off-by: Sandeep Paulraj Signed-off-by: Sneha Narnakaje --- drivers/mtd/nand/davinci_nand.c | 65 ++++++++++++++++++++++++++++++++++---- 1 files changed, 58 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index ba6940d..2ff0712 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -500,6 +500,49 @@ static struct nand_ecclayout hwecc4_small __initconst = { }, }; +/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash, + * storing ten ECC bytes plus the manufacturer's bad block marker byte, + * and not overlapping the default BBT markers. + */ +static struct nand_ecclayout hwecc4_2048 __initconst = { + .eccbytes = 40, + .eccpos = { /* 2 bytes at offset 0 hold the badblock markers */ + /* 4 bytes at offset 8 hold BBT header */ + /* 1 byte at offset 12 holds BBT version */ + /* 8 bytes at offset 16 hold JFFS2 clean markers */ + 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, + 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, }, + .oobfree = { + {.offset = 16, .length = 8, }, + {.offset = 64, }, + }, +}; + +/* An ECC layout for using 4-bit ECC with large-page (4096bytes) flash, + * storing ten ECC bytes plus the manufacturer's bad block marker byte, + * and not overlapping the default BBT markers. + */ +static struct nand_ecclayout hwecc4_4096 __initconst = { + .eccbytes = 80, + .eccpos = { /* 2 bytes at offset 0 hold the badblock markers */ + /* 4 bytes at offset 8 hold BBT header */ + /* 1 byte at offset 12 holds BBT version */ + /* 8 bytes at offset 16 hold JFFS2 clean markers */ + 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, + 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, + 74, 75, 76, 77, 78, 69, 80, 81, 82, 83, + 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, + 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, }, + .oobfree = { + {.offset = 16, .length = 8, }, + {.offset = 104, }, + }, +}; static int __init nand_davinci_probe(struct platform_device *pdev) { @@ -689,15 +732,23 @@ static int __init nand_davinci_probe(struct platform_device *pdev) info->mtd.oobsize - 16; goto syndrome_done; } + if (chunks == 4) { + info->ecclayout = hwecc4_2048; + info->ecclayout.oobfree[1].length = info->mtd.oobsize - + info->ecclayout.oobfree[1].offset; + info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST; + goto syndrome_done; + } + if (chunks == 8) { + info->ecclayout = hwecc4_4096; + info->ecclayout.oobfree[1].length = info->mtd.oobsize - + info->ecclayout.oobfree[1].offset; + info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST; + goto syndrome_done; + } - /* For large page chips we'll be wanting to use a - * not-yet-implemented mode that reads OOB data - * before reading the body of the page, to avoid - * the "infix OOB" model of NAND_ECC_HW_SYNDROME - * (and preserve manufacturer badblock markings). - */ dev_warn(&pdev->dev, "no 4-bit ECC support yet " - "for large page NAND\n"); + "for >4K page NAND\n"); ret = -EIO; goto err_scan;