Patchwork [SH] Cleanup endianness macros

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Submitter Oleg Endo
Date Oct. 27, 2013, 12:32 a.m.
Message ID <1382833969.2445.227.camel@yam-132-YW-E178-FTW>
Download mbox | patch
Permalink /patch/286324/
State New
Headers show

Comments

Oleg Endo - Oct. 27, 2013, 12:32 a.m.
Hello,

The attached patch adds a new macro TARGET_BIG_ENDIAN.  I think it's a
bit easier to read than !TARGET_LITTLE_ENDIAN.  Moreover, some not so
obvious looking uses of TARGET_LITTLE_ENDIAN for selecting MSW and LSW
register offsets are clarified by using new macros SH_REG_MSW_OFFSET and
SH_REG_LSW_OFFSET.
No functional changes.  Tested with make all-gcc.
OK for trunk?

Cheers,
Oleg

gcc/ChangeLog:
	* config/sh/sh.c (MSW, LSW): Move and rename macros to...
	* config/sh/sh.h (SH_REG_MSW_OFFSET, SH_REG_LSW_OFFSET):
	... here.
	(TARGET_BIG_ENDIAN): New macro.
	* config/sh/sh.md: Use it instead of !TARGET_LITTLE_ENDIAN.
	Use SH_REG_MSW_OFFSET and SH_REG_LSW_OFFSET.
	* config/sh/sh.c: Likewise.
	* config/sh/sh.h: Likewise.
Kaz Kojima - Oct. 27, 2013, 10:31 p.m.
Oleg Endo <oleg.endo@t-online.de> wrote:
> The attached patch adds a new macro TARGET_BIG_ENDIAN.  I think it's a
> bit easier to read than !TARGET_LITTLE_ENDIAN.  Moreover, some not so
> obvious looking uses of TARGET_LITTLE_ENDIAN for selecting MSW and LSW
> register offsets are clarified by using new macros SH_REG_MSW_OFFSET and
> SH_REG_LSW_OFFSET.
> No functional changes.  Tested with make all-gcc.
> OK for trunk?

OK.

Regards,
	kaz

Patch

Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(revision 204098)
+++ gcc/config/sh/sh.md	(working copy)
@@ -670,7 +670,7 @@ 
 	    (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
 		    (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_be>)
 	  (const_int 0)))]
-  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN"
+  "TARGET_SH1 && TARGET_BIG_ENDIAN"
   "tst	%0,%1"
   [(set_attr "type" "mt_group")])
 
@@ -761,7 +761,7 @@ 
 			    (match_operand:SI 3 "const_int_operand")) 3)
 	 (match_operand:SI 1 "const_int_operand")
 	 (match_operand:SI 2 "const_int_operand")))]
-  "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN
+  "TARGET_SH1 && TARGET_BIG_ENDIAN
    && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
       == (INTVAL (operands[3]) & 255)
    && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
@@ -2115,7 +2115,7 @@ 
 	(zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
 						       "general_extend_operand"
 						       "") 0)) 3)))]
-  "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
+  "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
    (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
   "")
@@ -3840,7 +3840,7 @@ 
       operands[0] = SUBREG_REG (operands[0]);
     }
   gcc_assert (REG_P (operands[0]));
-  if (! TARGET_LITTLE_ENDIAN)
+  if (TARGET_BIG_ENDIAN)
     offset += 8 - GET_MODE_SIZE (inmode);
   operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
 })
@@ -7733,11 +7733,11 @@ 
   rtx mem2
     = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
   insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
-					   regno + !! TARGET_LITTLE_ENDIAN),
+					       regno + SH_REG_MSW_OFFSET),
 				  mem2, operands[2]));
   add_reg_note (insn, REG_INC, operands[1]);
   insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
-					       regno + ! TARGET_LITTLE_ENDIAN),
+					       regno + SH_REG_LSW_OFFSET),
 				  change_address (mem, SFmode, NULL_RTX),
 				  operands[2]));
   DONE;
@@ -7755,8 +7755,8 @@ 
   int regno = true_regnum (operands[0]);
   rtx addr, insn;
   rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
-  rtx reg0 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  rtx reg1 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 0 : 1));
+  rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
+  rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
 
   operands[1] = copy_rtx (mem2);
   addr = XEXP (mem2, 0);
@@ -7821,8 +7821,8 @@ 
 {
   int regno = true_regnum (operands[1]);
   rtx insn, addr;
-  rtx reg0 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  rtx reg1 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 0 : 1));
+  rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
+  rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
 
   operands[0] = copy_rtx (operands[0]);
   PUT_MODE (operands[0], SFmode);
@@ -13160,7 +13160,7 @@ 
 			 (match_operand:SI 1 "immediate_operand" "")
 			 (match_operand:SI 2 "immediate_operand" ""))
 	(match_operand:SI 3 "general_operand" ""))]
-  "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN"
+  "TARGET_SH1 && TARGET_BIG_ENDIAN"
 {
   rtx addr_target, orig_address, shift_reg, qi_val;
   HOST_WIDE_INT bitsize, size, v = 0;
@@ -14522,7 +14522,7 @@ 
 	   (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
 	   (zero_extract:QI (not:QI (match_dup 2))
 			    (const_int 2) (const_int 6))])))]
-  "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
+  "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
   "mperm.w	%1, %N2, %0"
   [(set_attr "type" "arith_media")])
 
Index: gcc/config/sh/sh.c
===================================================================
--- gcc/config/sh/sh.c	(revision 204096)
+++ gcc/config/sh/sh.c	(working copy)
@@ -63,9 +63,6 @@ 
 
 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
 
-#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
-#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
-
 /* These are some macros to abstract register modes.  */
 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
 				 && ((HOST_WIDE_INT)(VALUE)) <= 511)
@@ -1208,12 +1205,12 @@ 
       if (REG_P (x) || GET_CODE (x) == SUBREG)
 	{
 	  regno = true_regnum (x);
-	  regno += FP_REGISTER_P (regno) ? 1 : LSW;
+	  regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET;
 	  fputs (reg_names[regno], (stream));
 	}
       else if (MEM_P (x))
 	{
-	  x = adjust_address (x, SImode, 4 * LSW);
+	  x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET);
 	  sh_print_operand_address (stream, XEXP (x, 0));
 	}
       else
@@ -1224,7 +1221,7 @@ 
 	  if (mode == VOIDmode)
 	    mode = DImode;
 	  if (GET_MODE_SIZE (mode) >= 8)
-	    sub = simplify_subreg (SImode, x, mode, 4 * LSW);
+	    sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET);
 	  if (sub)
 	    sh_print_operand (stream, sub, 0);
 	  else
@@ -1235,12 +1232,12 @@ 
       if (REG_P (x) || GET_CODE (x) == SUBREG)
 	{
 	  regno = true_regnum (x);
-	  regno += FP_REGISTER_P (regno) ? 0 : MSW;
+	  regno += FP_REGISTER_P (regno) ? 0 : SH_REG_MSW_OFFSET;
 	  fputs (reg_names[regno], (stream));
 	}
       else if (MEM_P (x))
 	{
-	  x = adjust_address (x, SImode, 4 * MSW);
+	  x = adjust_address (x, SImode, 4 * SH_REG_MSW_OFFSET);
 	  sh_print_operand_address (stream, XEXP (x, 0));
 	}
       else
@@ -1251,7 +1248,7 @@ 
 	  if (mode == VOIDmode)
 	    mode = DImode;
 	  if (GET_MODE_SIZE (mode) >= 8)
-	    sub = simplify_subreg (SImode, x, mode, 4 * MSW);
+	    sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_MSW_OFFSET);
 	  if (sub)
 	    sh_print_operand (stream, sub, 0);
 	  else
@@ -8261,8 +8258,8 @@ 
 	  emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
 	  mem = change_address (regbuf, SFmode, fpregs);
 	  emit_move_insn (mem,
-			  gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
-						- (TARGET_LITTLE_ENDIAN != 0)));
+			  gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode)
+					       + regno - SH_REG_MSW_OFFSET));
 	}
     }
   else
Index: gcc/config/sh/sh.h
===================================================================
--- gcc/config/sh/sh.h	(revision 204096)
+++ gcc/config/sh/sh.h	(working copy)
@@ -405,16 +405,21 @@ 
 
 /* Target machine storage layout.  */
 
+#define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN)
+
+#define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0)
+#define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1)
+
 /* Define this if most significant bit is lowest numbered
    in instructions that operate on numbered bit-fields.  */
 #define BITS_BIG_ENDIAN  0
 
 /* Define this if most significant byte of a word is the lowest numbered.  */
-#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
+#define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN
 
 /* Define this if most significant word of a multiword number is the lowest
    numbered.  */
-#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
+#define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN
 
 #define MAX_BITS_PER_WORD 64
 
@@ -1437,7 +1442,7 @@ 
 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
   ((MODE) == BLKmode \
    && TARGET_SHCOMPACT \
-   && ! TARGET_LITTLE_ENDIAN \
+   && TARGET_BIG_ENDIAN \
    && int_size_in_bytes (TYPE) > 4 \
    && int_size_in_bytes (TYPE) < 8)