From patchwork Fri Oct 25 09:49:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priyanka Jain X-Patchwork-Id: 286112 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D22E22C0354 for ; Fri, 25 Oct 2013 20:50:09 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7DF064A2AB; Fri, 25 Oct 2013 11:50:06 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VQCIMm1rRxku; Fri, 25 Oct 2013 11:50:06 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8D2BA4A29F; Fri, 25 Oct 2013 11:50:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D8B374A29F for ; Fri, 25 Oct 2013 11:49:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id z-Woveohc0iV for ; Fri, 25 Oct 2013 11:49:53 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe004.messaging.microsoft.com [213.199.154.207]) by theia.denx.de (Postfix) with ESMTPS id 6A10E4A29E for ; Fri, 25 Oct 2013 11:49:46 +0200 (CEST) Received: from mail38-am1-R.bigfish.com (10.3.201.233) by AM1EHSOBE004.bigfish.com (10.3.204.24) with Microsoft SMTP Server id 14.1.225.22; Fri, 25 Oct 2013 09:49:44 +0000 Received: from mail38-am1 (localhost [127.0.0.1]) by mail38-am1-R.bigfish.com (Postfix) with ESMTP id 8A2FF320390 for ; Fri, 25 Oct 2013 09:49:44 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail38-am1 (localhost.localdomain [127.0.0.1]) by mail38-am1 (MessageSwitch) id 1382694583514908_13351; Fri, 25 Oct 2013 09:49:43 +0000 (UTC) Received: from AM1EHSMHS010.bigfish.com (unknown [10.3.201.234]) by mail38-am1.bigfish.com (Postfix) with ESMTP id 71095A007A for ; Fri, 25 Oct 2013 09:49:43 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS010.bigfish.com (10.3.207.110) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 25 Oct 2013 09:49:36 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.158.2; Fri, 25 Oct 2013 09:49:34 +0000 Received: from b32167-VirtualBox.ap.freescale.net (B32167-02.ap.freescale.net [10.232.14.50]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r9P9nKpZ023697; Fri, 25 Oct 2013 02:49:32 -0700 From: Priyanka Jain To: Date: Fri, 25 Oct 2013 15:19:04 +0530 Message-ID: <1382694544-16133-1-git-send-email-Priyanka.Jain@freescale.com> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: Priyanka Jain , yorksun@freescale.com Subject: [U-Boot] [PATCH] powerpc/t1040qds: Add DDR Raw Timing support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de T1040QDS-D3 has dual-rank DDR: Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10). Add Raw Timing structure for this DDR. Typically SPD method is used for getting DDR parameter and calculating values for various DDR controller registers. But somentimes it may happen that SPD present on DDR may get accidently erased or is not working properly during initial bring-up. In that circumnstance, DDR raw timing structure can be use as fallback option for getting DDR parameters. Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain --- Based on u-boot-mpc85xx/next branch. board/freescale/t1040qds/ddr.c | 15 +++++++++++++++ board/freescale/t1040qds/ddr.h | 29 +++++++++++++++++++++++++++++ include/configs/T1040QDS.h | 1 + 3 files changed, 45 insertions(+), 0 deletions(-) diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 4fd17da..16ab829 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -15,6 +15,21 @@ DECLARE_GLOBAL_DATA_PTR; +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "RAW timing DDR"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index 8ee206e..4a4f76a 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -6,6 +6,35 @@ #ifndef __DDR_H__ #define __DDR_H__ +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 2147483648u, + .capacity = 4294967296u, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, /* ECC */ + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 1071, + .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 6000, + .trp_ps = 13125, + .tras_ps = 34000, + .trc_ps = 48125, + .trfc_ps = 260000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 35000, +}; + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 2738242..a8b32fe 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -168,6 +168,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD +#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE