[U-Boot,1/6,v2] powerpc:Add support of SPL non-relocation

Submitted by Prabhakar Kushwaha on Oct. 25, 2013, 4:38 a.m.

Details

Message ID 1382675901-24747-1-git-send-email-prabhakar@freescale.com
State Changes Requested
Delegated to: York Sun
Headers show

Commit Message

Prabhakar Kushwaha Oct. 25, 2013, 4:38 a.m.
Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.

To avoid relocation, move bss_section within SPL range.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 Based upon  git://git.denx.de/u-boot-mpc85xx.git branch next

 Changes for v2: Sending as it is

 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |   25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

Comments

Scott Wood Nov. 6, 2013, 1:24 a.m.
On Fri, 2013-10-25 at 10:08 +0530, Prabhakar Kushwaha wrote:
> Current SPL code base has BSS section placed after reset_vector. This means
> they have to relocate to use the global variables. This put an implicit
> requirement of having SPL size = Memory/2.
>
> To avoid relocation, move bss_section within SPL range.

Note that you still cannot access the BSS until after the "relocation"
phase, regardless of whether an actual relocation happens.  This is both
to ensure that the BSS has been cleared before you use it, and to avoid
introducing code that breaks in other situations.

> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
>  Based upon  git://git.denx.de/u-boot-mpc85xx.git branch next
> 
>  Changes for v2: Sending as it is
> 
>  arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |   25 ++++++++++++++++++++++++-
>  1 file changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> index bc13267..ffc6ad3 100644
> --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> @@ -57,13 +57,34 @@ SECTIONS
>  	. = ALIGN(8);
>  	__init_begin = .;
>  	__init_end = .;
> +#ifdef CONFIG_SKIP_RELOCATE_SPL

CONFIG symbols require documentation.  SPL config symbols should start
with CONFIG_SPL_.

I'm not sure you need a new config symbol, though.  Couldn't you do
something like:

#if CONFIG_SPL_TEXT_BASE == CONFIG_SPL_PAYLOAD_DEST

...where CONFIG_SPL_PAYLOAD_DEST replaces the various
CONFIG_SYS_{NAND,MMC,SPI}_U_BOOT_DST.

> +	/*
> +	 * Make sure that the bss segment isn't linked at 0x0, otherwise its
> +	 * address won't be updated during relocation fixups.
> +	 */
> +	. |= 0x10;

Why do you need this if BSS isn't being located after the reset vector?

>  /* FIXME for non-NAND SPL */
>  #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
> -	.bootpg ADDR(.text) + 0x1000 :
> +#ifndef BOOT_PAGE_OFFSET
> +#define BOOT_PAGE_OFFSET 0x1000
> +#endif
> +	.bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
>  	{
>  		arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
>  	}
>
> +#ifndef RESET_VECTOR_OFFSET
>  #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
> +#endif

This seems unrelated and has no explanation.

-Scott

Patch hide | download patch | download mbox

diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index bc13267..ffc6ad3 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,13 +57,34 @@  SECTIONS
 	. = ALIGN(8);
 	__init_begin = .;
 	__init_end = .;
+#ifdef CONFIG_SKIP_RELOCATE_SPL
+	/*
+	 * Make sure that the bss segment isn't linked at 0x0, otherwise its
+	 * address won't be updated during relocation fixups.
+	 */
+	. |= 0x10;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : {
+		*(.sbss*)
+		*(.bss*)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+#endif
 /* FIXME for non-NAND SPL */
 #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
-	.bootpg ADDR(.text) + 0x1000 :
+#ifndef BOOT_PAGE_OFFSET
+#define BOOT_PAGE_OFFSET 0x1000
+#endif
+	.bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
 	{
 		arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
 	}
+#ifndef RESET_VECTOR_OFFSET
 #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#endif
 #elif defined(CONFIG_FSL_ELBC)
 #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
 #else
@@ -80,6 +101,7 @@  SECTIONS
 	} = 0xffff
 #endif
 
+#ifndef CONFIG_SKIP_RELOCATE_SPL
 	/*
 	 * Make sure that the bss segment isn't linked at 0x0, otherwise its
 	 * address won't be updated during relocation fixups.
@@ -94,4 +116,5 @@  SECTIONS
 	}
 	. = ALIGN(4);
 	__bss_end = .;
+#endif
 }