From patchwork Wed Oct 23 07:41:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Francois Moine X-Patchwork-Id: 285538 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EAB2C2C025E for ; Wed, 23 Oct 2013 18:52:56 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VYt5L-0003A6-QM; Wed, 23 Oct 2013 07:42:32 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VYt4g-0006TW-G6; Wed, 23 Oct 2013 07:41:50 +0000 Received: from smtp4-g21.free.fr ([2a01:e0c:1:1599::13]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VYt4a-0006RM-20 for linux-arm-kernel@lists.infradead.org; Wed, 23 Oct 2013 07:41:45 +0000 Received: from armhf (unknown [IPv6:2a01:e35:2f5c:9de0:212:bfff:fe1e:9ce4]) by smtp4-g21.free.fr (Postfix) with ESMTP id 1DE264C8255; Wed, 23 Oct 2013 09:41:13 +0200 (CEST) Date: Wed, 23 Oct 2013 09:41:49 +0200 From: Jean-Francois Moine To: linux-arm-kernel@lists.infradead.org Subject: ]PATCH 9/10] drm/i2c: tda998x: fix some video errors Message-ID: <20131023094149.127451db@armhf> X-Mailer: Claws Mail 3.9.2 (GTK+ 2.24.21; arm-unknown-linux-gnueabihf) Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131023_034144_814063_D8227A73 X-CRM114-Status: GOOD ( 17.15 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (moinejf[at]free.fr) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Jason Cooper , David Airlie , Rob Clark , Darren Etheridge , Russell King , Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org This patch fixes some video errors: - shift and set the repeat PLL value in range 0..3 - set the quantization range to RGB/YUV instead of full - set 0 the register ENABLE_SPACE to fill the active space - set the 'toggle enable' bit when needed - move the TBG_CNTRL_0 setting as the last register set - don't set SYNC_ONCE Signed-off-by: Jean-Francois Moine --- drivers/gpu/drm/i2c/tda998x_drv.c | 28 ++++++++++++++-------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c index e19a554..b0eecee 100644 --- a/drivers/gpu/drm/i2c/tda998x_drv.c +++ b/drivers/gpu/drm/i2c/tda998x_drv.c @@ -224,7 +224,7 @@ struct tda998x_priv { # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ -# define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0) +# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ # define PLL_SERIAL_3_SRL_CCIR (1 << 0) @@ -975,6 +975,11 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, } div = 148500 / mode->clock; + if (div != 0) { + div--; + if (div > 3) + div = 3; + } /* mute the audio FIFO: */ reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); @@ -995,7 +1000,9 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); reg_write(priv, REG_SERIALIZER, 0); - reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); + + /* video quantization range = 0: full, 1: RGB/YUV, 2: YUV */ + reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(1)); /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ rep = 0; @@ -1013,7 +1020,7 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, /* set BIAS tmds value: */ reg_write(priv, REG_ANA_GENERAL, 0x09); - reg_write(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); + reg_write(priv, REG_TBG_CNTRL_0, 0); /* * Sync on rising HSYNC/VSYNC @@ -1065,22 +1072,19 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, if (priv->rev == TDA19988) { /* let incoming pixels fill the active space (if any) */ - reg_write(priv, REG_ENABLE_SPACE, 0x01); + reg_write(priv, REG_ENABLE_SPACE, 0x00); } } - /* must be last register set: */ - reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); - /* * Always generate sync polarity relative to input sync and * revert input stage toggled sync at output stage */ - reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; + reg = TBG_CNTRL_1_DWIN_DIS; if (mode->flags & DRM_MODE_FLAG_NHSYNC) - reg |= TBG_CNTRL_1_H_TGL; + reg |= TBG_CNTRL_1_H_TGL | TBG_CNTRL_1_TGL_EN; if (mode->flags & DRM_MODE_FLAG_NVSYNC) - reg |= TBG_CNTRL_1_V_TGL; + reg |= TBG_CNTRL_1_V_TGL | TBG_CNTRL_1_TGL_EN; reg_write(priv, REG_TBG_CNTRL_1, reg); /* Only setup the info frames if the sink is HDMI */ @@ -1096,6 +1100,10 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, if (priv->audio) tda998x_configure_audio(priv, mode, &priv->params); } + + /* must be last register set: */ + reg_write(priv, REG_TBG_CNTRL_0, 0); +/* TBG_CNTRL_0_SYNC_ONCE does not work after dpms off/on */ } static enum drm_connector_status