| Submitter | mware@internode.on.net |
|---|---|
| Date | June 11, 2009, 3:01 a.m. |
| Message ID | <38410.1244689279@internode.on.net> |
| Download | mbox | patch |
| Permalink | /patch/28547/ |
| State | Accepted |
| Delegated to: | Kumar Gala |
| Headers | show |
Comments
On Jun 10, 2009, at 10:01 PM, mware@internode.on.net wrote: > Currently the fsl,*lbc devices support 8 banks (ie OR and BR > registers). > This is adequate for most pq2 and pq3 processors, but not the > MPC8280 which > has 12 banks. > > Signed-Off-By: Mark Ware <mware@elphinstone.net> > --- > arch/powerpc/include/asm/fsl_lbc.h | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) fsl_lbc is not applicable to the MPC8280. Its only used for MPC83xx, MPC85xx, and MPC86xx. - k
Patch
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 63a4f77..1b5a210 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -95,8 +95,8 @@ struct fsl_lbc_bank { }; struct fsl_lbc_regs { - struct fsl_lbc_bank bank[8]; - u8 res0[0x28]; + struct fsl_lbc_bank bank[12]; + u8 res0[0x8]; __be32 mar; /**< UPM Address Register */ u8 res1[0x4]; __be32 mamr; /**< UPMA Mode Register */
Currently the fsl,*lbc devices support 8 banks (ie OR and BR registers). This is adequate for most pq2 and pq3 processors, but not the MPC8280 which has 12 banks. Signed-Off-By: Mark Ware <mware@elphinstone.net> --- arch/powerpc/include/asm/fsl_lbc.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) -- 1.5.6.5