From patchwork Mon Oct 21 23:28:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Otavio Salvador X-Patchwork-Id: 285301 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D65392C00CE for ; Tue, 22 Oct 2013 10:37:19 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 70B494A1F5; Tue, 22 Oct 2013 01:37:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9x4LUUU+b5mh; Tue, 22 Oct 2013 01:37:18 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4C8A54A218; Tue, 22 Oct 2013 01:37:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 779D04A218 for ; Tue, 22 Oct 2013 01:37:06 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HR7TGIr7mn3k for ; Tue, 22 Oct 2013 01:37:01 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ve0-f179.google.com (mail-ve0-f179.google.com [209.85.128.179]) by theia.denx.de (Postfix) with ESMTPS id 9349B4A1F5 for ; Tue, 22 Oct 2013 01:36:56 +0200 (CEST) Received: by mail-ve0-f179.google.com with SMTP id cz12so4082918veb.10 for ; Mon, 21 Oct 2013 16:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:mime-version:content-type :content-transfer-encoding:organization; bh=h7dmV2tt0RJXEmKek+DxTM6i0zfYvKkevXdLuESDCPI=; b=cWwTKXBoRkMiOPc6ufduOMu5as+ocKbgOpWSSsR3N5ylTBhrbMDvn3AU/mKPwbLv+v 3Qez6xM1gb4UBxoPHdJMXED4K3H7pp/yxFBrbfT1BWwjQXurzj+AueOW047blc7/xBDT b2L92jtmBzdnd28hAXgjUrL1X+b2QBodjEFhLdBR4I9spSdz68iwtcF3PIeYVS5FhJUY OTFCOo4tFd2vrnSNo527QeeEAaE1yp1/S7TVx42U8vEhGFeFQrF6Pu/skuxohIYc1Kyj cfzLnTytZAHWxrkprCJzemkuYU26jNvyFt1YpR0OCemFh23AbB7kFE66KCX/j4WpxMmQ x0OQ== X-Received: by 10.52.165.131 with SMTP id yy3mr2361881vdb.25.1382398142684; Mon, 21 Oct 2013 16:29:02 -0700 (PDT) Received: from nano.lab.ossystems.com.br ([177.194.208.225]) by mx.google.com with ESMTPSA id k17sm23989698vdh.7.2013.10.21.16.28.58 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Oct 2013 16:29:01 -0700 (PDT) Received: by nano.lab.ossystems.com.br (Postfix, from userid 1000) id 23A8D16AC1177; Mon, 21 Oct 2013 21:28:54 -0200 (BRST) From: Otavio Salvador To: U-Boot Mailing List Date: Mon, 21 Oct 2013 21:28:46 -0200 Message-Id: <1382398126-7551-1-git-send-email-otavio@ossystems.com.br> X-Mailer: git-send-email 1.8.4.rc3 MIME-Version: 1.0 Organization: O.S. Systems Software LTDA. Cc: Fabio Estevam , Marek Vasut , Otavio Salvador Subject: [U-Boot] [RESEND PATCH] imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau , Fabio Estevam and Eric Bénard for helping to properly trace this down. Signed-off-by: Otavio Salvador --- arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dc2b3ef..dec11a1 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -63,6 +63,8 @@ typedef u64 iomux_v3_cfg_t; #define MUX_SEL_INPUT_SHIFT 59 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ + MUX_MODE_SHIFT) #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \