diff mbox

[U-Boot] powerpc/c29xpcie: reverse CPLD register bit

Message ID 1382346936-25840-1-git-send-email-Po.Liu@freescale.com
State Deferred
Delegated to: York Sun
Headers show

Commit Message

Po Liu Oct. 21, 2013, 9:15 a.m. UTC 
The CPLD registers MSB is powerpc's LSB, and LSB is powerpc's MSB.
It is not convinient for understand. Reverse the value when read
write to the CPLD registers.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
This patch after
http://patchwork.ozlabs.org/patch/278079/
[U-Boot,v2] powerpc/c29xpcie: add DDR ECC on off config setting

 board/freescale/c29xpcie/c29xpcie.c |  3 +-
 board/freescale/c29xpcie/cpld.c     | 94 +++++++++++++++++++++++++------------
 board/freescale/c29xpcie/cpld.h     | 21 +++++++--
 board/freescale/c29xpcie/ddr.c      |  4 +-
 4 files changed, 83 insertions(+), 39 deletions(-)
diff mbox

Patch

diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index 48c4b30..e22c774 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -28,10 +28,9 @@  DECLARE_GLOBAL_DATA_PTR;
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 
 	printf("Board: %sPCIe, ", cpu->name);
-	printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
+	printf("CPLD Ver: %x.%x\n", CPLD_READ(hwver), CPLD_READ(cpldver));
 
 	return 0;
 }
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index 5cbccff..beaba63 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -20,31 +20,63 @@ 
 #include <asm/io.h>
 
 #include "cpld.h"
+
+static u8 rev_bit(u8 val)
+{
+	u8 rev_val;
+	int i;
+
+	rev_val = val & 1;
+	for (i = 1; i <= 7; i++) {
+		val >>= 1;
+		rev_val <<= 1;
+		rev_val |= val & 1;
+	}
+
+	return rev_val;
+}
+
+static u8 __cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return rev_bit(in_8(p + reg));
+}
+
+u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
+
+static void __cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, rev_bit(value));
+}
+
+void cpld_write(unsigned int reg, u8 value)
+	__attribute__((weak, alias("__cpld_write")));
+
 /**
  * Set the boot bank to the alternate bank
  */
-void cpld_set_altbank(u8 banksel)
+void __cpld_set_altbank(u8 banksel)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-	u8 reg11;
-
-	reg11 = in_8(&cpld_data->flhcsr);
+	u8 reg11 = CPLD_READ(flhcsr);
 
 	switch (banksel) {
 	case 1:
-		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+		CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)
 			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
 		break;
 	case 2:
-		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+		CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)
 			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
 		break;
 	case 3:
-		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+		CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)
 			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
 		break;
 	case 4:
-		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+		CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)
 			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
 		break;
 	default:
@@ -56,35 +88,39 @@  void cpld_set_altbank(u8 banksel)
 	do_reset(NULL, 0, 0, NULL);
 }
 
+void cpld_set_altbank(u8 banksel)
+	__attribute__((weak, alias("__cpld_set_altbank")));
+
 /**
  * Set the boot bank to the default bank
  */
-void cpld_set_defbank(void)
+void __cpld_set_defbank(void)
 {
-	cpld_set_altbank(4);
+	__cpld_set_altbank(4);
 }
 
+void cpld_set_defbank(void)
+	__attribute__((weak, alias("__cpld_set_defbank")));
+
 #ifdef DEBUG
 static void cpld_dump_regs(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
-	printf("chipid1		= 0x%02x\n", in_8(&cpld_data->chipid1));
-	printf("chipid2		= 0x%02x\n", in_8(&cpld_data->chipid2));
-	printf("hwver		= 0x%02x\n", in_8(&cpld_data->hwver));
-	printf("cpldver		= 0x%02x\n", in_8(&cpld_data->cpldver));
-	printf("rstcon		= 0x%02x\n", in_8(&cpld_data->rstcon));
-	printf("flhcsr		= 0x%02x\n", in_8(&cpld_data->flhcsr));
-	printf("wdcsr		= 0x%02x\n", in_8(&cpld_data->wdcsr));
-	printf("wdkick		= 0x%02x\n", in_8(&cpld_data->wdkick));
-	printf("fancsr		= 0x%02x\n", in_8(&cpld_data->fancsr));
-	printf("ledcsr		= 0x%02x\n", in_8(&cpld_data->ledcsr));
-	printf("misc		= 0x%02x\n", in_8(&cpld_data->misccsr));
-	printf("bootor		= 0x%02x\n", in_8(&cpld_data->bootor));
-	printf("bootcfg1	= 0x%02x\n", in_8(&cpld_data->bootcfg1));
-	printf("bootcfg2	= 0x%02x\n", in_8(&cpld_data->bootcfg2));
-	printf("bootcfg3	= 0x%02x\n", in_8(&cpld_data->bootcfg3));
-	printf("bootcfg4	= 0x%02x\n", in_8(&cpld_data->bootcfg4));
+	printf("chipid1		= 0x%02x\n", CPLD_READ(chipid1));
+	printf("chipid2		= 0x%02x\n", CPLD_READ(chipid2));
+	printf("hwver		= 0x%02x\n", CPLD_READ(hwver));
+	printf("cpldver		= 0x%02x\n", CPLD_READ(cpldver));
+	printf("rstcon		= 0x%02x\n", CPLD_READ(rstcon));
+	printf("flhcsr		= 0x%02x\n", CPLD_READ(flhcsr));
+	printf("wdcsr		= 0x%02x\n", CPLD_READ(wdcsr));
+	printf("wdkick		= 0x%02x\n", CPLD_READ(wdkick));
+	printf("fancsr		= 0x%02x\n", CPLD_READ(fancsr));
+	printf("ledcsr		= 0x%02x\n", CPLD_READ(ledcsr));
+	printf("misc		= 0x%02x\n", CPLD_READ(misccsr));
+	printf("bootor		= 0x%02x\n", CPLD_READ(bootor));
+	printf("bootcfg1	= 0x%02x\n", CPLD_READ(bootcfg1));
+	printf("bootcfg2	= 0x%02x\n", CPLD_READ(bootcfg2));
+	printf("bootcfg3	= 0x%02x\n", CPLD_READ(bootcfg3));
+	printf("bootcfg4	= 0x%02x\n", CPLD_READ(bootcfg4));
 	putc('\n');
 }
 #endif
diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h
index 20862a3..af3b1be 100644
--- a/board/freescale/c29xpcie/cpld.h
+++ b/board/freescale/c29xpcie/cpld.h
@@ -32,9 +32,20 @@  struct cpld_data {
 	u8 bootcfg4;	/* 0x1b - Boot configure 4 Register */
 };
 
-#define CPLD_BANKSEL_EN		0x02
-#define CPLD_BANKSEL_MASK	0x3f
-#define CPLD_SELECT_BANK1	0xc0
-#define CPLD_SELECT_BANK2	0x80
-#define CPLD_SELECT_BANK3	0x40
+/* Pointer to the CPLD register set */
+#define cpld ((struct cpld_data *)CONFIG_SYS_CPLD_BASE)
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_BANKSEL_EN		0x40
+#define CPLD_BANKSEL_MASK	0xfc
+#define CPLD_SELECT_BANK1	0x03
+#define CPLD_SELECT_BANK2	0x01
+#define CPLD_SELECT_BANK3	0x02
 #define CPLD_SELECT_BANK4	0x00
+#define C29XPCIE_HARDWARE_REVA  0x02
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value) cpld_write(offsetof(struct cpld_data, reg), \
+						value)
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index 4077ed9..0d00b63 100644
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -11,7 +11,6 @@ 
 
 #include "cpld.h"
 
-#define C29XPCIE_HARDWARE_REVA	0x40
 /*
  * Micron MT41J128M16HA-15E
  * */
@@ -64,7 +63,6 @@  void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 	int i;
 
 	popts->clk_adjust = 2;
@@ -84,7 +82,7 @@  void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->trwt_override = 1;
 	popts->trwt = 0;
 
-	if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
+	if (CPLD_READ(hwver) == C29XPCIE_HARDWARE_REVA)
 		popts->ecc_mode = 0;
 
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {