Patchwork [MIPS] Add bswap patterns

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Submitter Richard Sandiford
Date Oct. 20, 2013, 7:17 a.m.
Message ID <87iows5s2g.fsf@talisman.default>
Download mbox | patch
Permalink /patch/284952/
State New
Headers show

Comments

Richard Sandiford - Oct. 20, 2013, 7:17 a.m.
Noticed the other day that we'd never added bswap patterns for WSBH & co.

Tested on mips64-linux-gnu with --with-arch=mips64r2 and applied.

Richard


gcc/
	* config/mips/mips.h (ISA_HAS_WSBH): Define.
	* config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New
	constants.
	(bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns.

gcc/testsuite/
	* gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c,
	gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c,
	gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests.

Patch

Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h	2013-10-16 20:38:57.977088830 +0100
+++ gcc/config/mips/mips.h	2013-10-19 11:32:47.636342587 +0100
@@ -972,6 +972,11 @@  #define ISA_HAS_ROR		((ISA_MIPS32R2				\
 				  || TARGET_SMARTMIPS)			\
 				 && !TARGET_MIPS16)
 
+/* ISA has the WSBH (word swap bytes within halfwords) instruction.
+   64-bit targets also provide DSBH and DSHD.  */
+#define ISA_HAS_WSBH		((ISA_MIPS32R2 || ISA_MIPS64R2)		\
+				 && !TARGET_MIPS16)
+
 /* ISA has data prefetch instructions.  This controls use of 'pref'.  */
 #define ISA_HAS_PREFETCH	((ISA_MIPS4				\
 				  || TARGET_LOONGSON_2EF		\
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md	2013-10-16 20:38:57.977088830 +0100
+++ gcc/config/mips/mips.md	2013-10-19 11:36:21.984285902 +0100
@@ -74,6 +74,11 @@  (define_c_enum "unspec" [
   UNSPEC_STORE_LEFT
   UNSPEC_STORE_RIGHT
 
+  ;; Integer operations that are too cumbersome to describe directly.
+  UNSPEC_WSBH
+  UNSPEC_DSBH
+  UNSPEC_DSHD
+
   ;; Floating-point moves.
   UNSPEC_LOAD_LOW
   UNSPEC_LOAD_HIGH
@@ -5358,6 +5363,56 @@  (define_insn "rotr<mode>3"
 }
   [(set_attr "type" "shift")
    (set_attr "mode" "<MODE>")])
+
+(define_insn "bswaphi2"
+  [(set (match_operand:HI 0 "register_operand" "=d")
+	(bswap:HI (match_operand:HI 1 "register_operand" "d")))]
+  "ISA_HAS_WSBH"
+  "wsbh\t%0,%1"
+  [(set_attr "type" "shift")])
+
+(define_insn_and_split "bswapsi2"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(bswap:SI (match_operand:SI 1 "register_operand" "d")))]
+  "ISA_HAS_WSBH && ISA_HAS_ROR"
+  "#"
+  ""
+  [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))
+   (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
+  ""
+  [(set_attr "insn_count" "2")])
+
+(define_insn_and_split "bswapdi2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(bswap:DI (match_operand:DI 1 "register_operand" "d")))]
+  "TARGET_64BIT && ISA_HAS_WSBH"
+  "#"
+  ""
+  [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH))
+   (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))]
+  ""
+  [(set_attr "insn_count" "2")])
+
+(define_insn "wsbh"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))]
+  "ISA_HAS_WSBH"
+  "wsbh\t%0,%1"
+  [(set_attr "type" "shift")])
+
+(define_insn "dsbh"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))]
+  "TARGET_64BIT && ISA_HAS_WSBH"
+  "dsbh\t%0,%1"
+  [(set_attr "type" "shift")])
+
+(define_insn "dshd"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))]
+  "TARGET_64BIT && ISA_HAS_WSBH"
+  "dshd\t%0,%1"
+  [(set_attr "type" "shift")])
 
 ;;
 ;;  ....................
Index: gcc/testsuite/gcc.target/mips/bswap-1.c
===================================================================
--- /dev/null	2013-10-13 08:29:45.608935301 +0100
+++ gcc/testsuite/gcc.target/mips/bswap-1.c	2013-10-19 11:30:01.551867196 +0100
@@ -0,0 +1,10 @@ 
+/* { dg-options "isa_rev>=2" } */
+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
+
+NOMIPS16 unsigned short
+foo (unsigned short x)
+{
+  return ((x << 8) & 0xff00) | ((x >> 8) & 0xff);
+}
+
+/* { dg-final { scan-assembler "\twsbh\t" } } */
Index: gcc/testsuite/gcc.target/mips/bswap-2.c
===================================================================
--- /dev/null	2013-10-13 08:29:45.608935301 +0100
+++ gcc/testsuite/gcc.target/mips/bswap-2.c	2013-10-19 11:30:01.551867196 +0100
@@ -0,0 +1,9 @@ 
+/* { dg-options "isa_rev>=2" } */
+
+NOMIPS16 unsigned short
+foo (unsigned short x)
+{
+  return __builtin_bswap16 (x);
+}
+
+/* { dg-final { scan-assembler "\twsbh\t" } } */
Index: gcc/testsuite/gcc.target/mips/bswap-3.c
===================================================================
--- /dev/null	2013-10-13 08:29:45.608935301 +0100
+++ gcc/testsuite/gcc.target/mips/bswap-3.c	2013-10-19 11:30:01.552867204 +0100
@@ -0,0 +1,14 @@ 
+/* { dg-options "isa_rev>=2" } */
+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
+
+NOMIPS16 unsigned int
+foo (unsigned int x)
+{
+  return (((x << 24) & 0xff000000)
+	  | ((x << 8) & 0xff0000)
+	  | ((x >> 8) & 0xff00)
+	  | ((x >> 24) & 0xff));
+}
+
+/* { dg-final { scan-assembler "\twsbh\t" } } */
+/* { dg-final { scan-assembler "\tror\t" } } */
Index: gcc/testsuite/gcc.target/mips/bswap-4.c
===================================================================
--- /dev/null	2013-10-13 08:29:45.608935301 +0100
+++ gcc/testsuite/gcc.target/mips/bswap-4.c	2013-10-19 11:30:01.552867204 +0100
@@ -0,0 +1,10 @@ 
+/* { dg-options "isa_rev>=2" } */
+
+NOMIPS16 unsigned int
+foo (unsigned int x)
+{
+  return __builtin_bswap32 (x);
+}
+
+/* { dg-final { scan-assembler "\twsbh\t" } } */
+/* { dg-final { scan-assembler "\tror\t" } } */
Index: gcc/testsuite/gcc.target/mips/bswap-5.c
===================================================================
--- /dev/null	2013-10-13 08:29:45.608935301 +0100
+++ gcc/testsuite/gcc.target/mips/bswap-5.c	2013-10-19 11:40:43.254634585 +0100
@@ -0,0 +1,20 @@ 
+/* { dg-options "isa_rev>=2 -mgp64" } */
+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
+
+typedef unsigned long long uint64_t;
+
+NOMIPS16 uint64_t
+foo (uint64_t x)
+{
+  return (((x << 56) & 0xff00000000000000ull)
+	  | ((x << 40) & 0xff000000000000ull)
+	  | ((x << 24) & 0xff0000000000ull)
+	  | ((x << 8) & 0xff00000000ull)
+	  | ((x >> 8) & 0xff000000)
+	  | ((x >> 24) & 0xff0000)
+	  | ((x >> 40) & 0xff00)
+	  | ((x >> 56) & 0xff));
+}
+
+/* { dg-final { scan-assembler "\tdsbh\t" } } */
+/* { dg-final { scan-assembler "\tdshd\t" } } */
Index: gcc/testsuite/gcc.target/mips/bswap-6.c
===================================================================
--- /dev/null	2013-10-13 08:29:45.608935301 +0100
+++ gcc/testsuite/gcc.target/mips/bswap-6.c	2013-10-19 11:41:19.042969469 +0100
@@ -0,0 +1,12 @@ 
+/* { dg-options "isa_rev>=2 -mgp64" } */
+
+typedef unsigned long long uint64_t;
+
+NOMIPS16 uint64_t
+foo (uint64_t x)
+{
+  return __builtin_bswap64 (x);
+}
+
+/* { dg-final { scan-assembler "\tdsbh\t" } } */
+/* { dg-final { scan-assembler "\tdshd\t" } } */