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[U-Boot,1/3] fpga: zynqpl: Add dcache flush support

Message ID b73c1028229b0e5ba75a422478f10e3f0e1e61c1.1382023331.git.michal.simek@xilinx.com
State Accepted
Delegated to: Michal Simek
Headers show

Commit Message

Michal Simek Oct. 17, 2013, 3:22 p.m. UTC 
From: Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki@xilinx.com>

Buffers must be cache and dma aligned.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/fpga/zynqpl.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

--
1.8.2.3
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Patch

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 717c039..f2f49b5 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -177,8 +177,8 @@  int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		return FPGA_FAIL;
 	}

-	if ((u32)buf_start & 0x3) {
-		u32 *new_buf = (u32 *)((u32)buf & ~0x3);
+	if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
+		u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);

 		printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
 		       (u32)buf_start, (u32)new_buf, swap);
@@ -284,6 +284,10 @@  int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
 	debug("%s: Size = %zu\n", __func__, bsize);

+	/* flush(clean & invalidate) d-cache range buf */
+	flush_dcache_range((u32)buf, (u32)buf +
+			   roundup(bsize, ARCH_DMA_MINALIGN));
+
 	/* Set up the transfer */
 	writel((u32)buf | 1, &devcfg_base->dma_src_addr);
 	writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);