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[U-Boot,V2] ARM: OMAP5: DDR3: Change io settings

Message ID 1381930334-32649-1-git-send-email-r.sricharan@ti.com
State Superseded
Delegated to: Tom Rini
Headers show

Commit Message

SRICHARAN R Oct. 16, 2013, 1:32 p.m. UTC 
The DDR DQ lines are enabled with weak pull. So the DQ line was not staying at Vref
when IDLE (retreats to ground) and because of this there were extra transitions
and noise. So change from 0x64656465 to 0x64646464 to remove the weak pull.

Also internal VREF_DQOUT is set to 0. This has to enabled as well.

With the above two changes better memory stability was observed with extended 
temperature ranges around 100C

Signed-off-by: Sricharan R <r.sricharan@ti.com>
---
[V2] Added more descriptive commit log

 arch/arm/include/asm/arch-omap5/omap.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 414d37a..3c2306f 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -145,9 +145,9 @@  struct s32ktimer {
 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE				0x0
 
 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
-#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
-#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
 
 #define EFUSE_1 0x45145100