From patchwork Tue Oct 15 16:06:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 283721 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E4A7F2C032D for ; Wed, 16 Oct 2013 03:07:10 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759533Ab3JOQHH (ORCPT ); Tue, 15 Oct 2013 12:07:07 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:55287 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759122Ab3JOQHF (ORCPT ); Tue, 15 Oct 2013 12:07:05 -0400 Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3czhNS2R6Gz3hj5N; Tue, 15 Oct 2013 18:07:04 +0200 (CEST) X-Auth-Info: 0cYCOkm5vGiKP4oTFd0EiEtgfrWyxsrYCw38PlOI6gw= Received: from chi.lan (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3czhNR4YB5zbbl1; Tue, 15 Oct 2013 18:07:03 +0200 (CEST) From: Marek Vasut To: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Marek Vasut , Bjorn Helgaas , Frank Li , Jingoo Han , Mohit KUMAR , Pratyush Anand , Richard Zhu , Sascha Hauer , Sean Cross , Shawn Guo , Siva Reddy Kallam , Srikanth T Shivanand , Tim Harvey , Troy Kisky , Yinghai Lu Subject: [PATCH 5/6] PCI: imx6: Force Gen1 operation Date: Tue, 15 Oct 2013 18:06:39 +0200 Message-Id: <1381853200-5534-6-git-send-email-marex@denx.de> X-Mailer: git-send-email 1.8.4.rc3 In-Reply-To: <1381853200-5534-1-git-send-email-marex@denx.de> References: <1381853200-5534-1-git-send-email-marex@denx.de> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Without forcing the PCIe core into Gen1 operation, the PCIe switch attached directly to the PCIe port is not recognised at all. The PCIe switch is Gen2 capable to make this issue even more puzzling. Signed-off-by: Marek Vasut Cc: Bjorn Helgaas Cc: Frank Li Cc: Jingoo Han Cc: Mohit KUMAR Cc: Pratyush Anand Cc: Richard Zhu Cc: Sascha Hauer Cc: Sean Cross Cc: Shawn Guo Cc: Siva Reddy Kallam Cc: Srikanth T Shivanand Cc: Tim Harvey Cc: Troy Kisky Cc: Yinghai Lu --- drivers/pci/host/pci-imx6.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index ca8c5de..8402e9a 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -321,6 +321,7 @@ static void imx6_pcie_host_init(struct pcie_port *pp) { int count = 0; struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); + uint32_t tmp; imx6_pcie_assert_core_reset(pp); @@ -330,13 +331,23 @@ static void imx6_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); + /* + * FIXME: + * Force Gen1 operation. In case the IP block is in Gen2 operation + * mode, it does not detect the PCIe switch at all. + */ + tmp = readl(pp->dbi_base + 0x7c); + tmp &= ~0xf; + tmp |= 0x1; + writel(tmp, pp->dbi_base + 0x7c); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); while (!dw_pcie_link_up(pp)) { usleep_range(100, 1000); count++; - if (count >= 10) { + if (count >= 200) { dev_err(pp->dev, "phy link never came up\n"); dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",