From patchwork Tue Jun 9 18:53:59 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nate Case X-Patchwork-Id: 28345 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 5A7ACB70D9 for ; Wed, 10 Jun 2009 04:54:42 +1000 (EST) Received: by ozlabs.org (Postfix) id 466F4DDD1C; Wed, 10 Jun 2009 04:54:42 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (bilbo.ozlabs.org [203.10.76.25]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "bilbo.ozlabs.org", Issuer "CAcert Class 3 Root" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 3CADBDDD1B for ; Wed, 10 Jun 2009 04:54:42 +1000 (EST) Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by bilbo.ozlabs.org (Postfix) with ESMTP id 17DCDB73AE for ; Wed, 10 Jun 2009 04:54:19 +1000 (EST) Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 781DDB70D7 for ; Wed, 10 Jun 2009 04:54:12 +1000 (EST) Received: by ozlabs.org (Postfix) id 5D544DDD0C; Wed, 10 Jun 2009 04:54:12 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from xes-mad.com (xes-mad.com [216.165.139.214]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 11FE6DDD04 for ; Wed, 10 Jun 2009 04:54:10 +1000 (EST) Received: from [10.52.0.27] (natec.xes-mad.com [10.52.0.27]) by xes-mad.com (8.13.8/8.13.8) with ESMTP id n59Irxnx026441; Tue, 9 Jun 2009 13:54:00 -0500 Subject: Re: [PATCH -next] powerpc/85xx: Add support for X-ES MPC85xx boards From: Nate Case To: Kumar Gala In-Reply-To: <2AF4BA69-D05A-4D2E-BD32-5E1C93ACF445@kernel.crashing.org> References: <1244499228-18602-1-git-send-email-ncase@xes-inc.com> <2AF4BA69-D05A-4D2E-BD32-5E1C93ACF445@kernel.crashing.org> Organization: Extreme Engineering Solutions, Inc. Date: Tue, 09 Jun 2009 13:53:59 -0500 Message-Id: <1244573639.29684.1536.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 X-Virus-Scanned: ClamAV 0.94.2/9441/Mon Jun 8 23:35:21 2009 on mail.xes-mad.com X-Virus-Status: Clean X-Spam-Status: No, score=-6.2 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00, XES_TECH_CPU autolearn=ham version=3.2.5 X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on mail.xes-mad.com Cc: linuxppc-dev@ozlabs.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org On Mon, 2009-06-08 at 17:52 -0500, Kumar Gala wrote: > > +static void xes_mpc85xx_configure_l1(void) > > +{ [snip] > > I'd prefer we move this into __setup_cpu_e500v1/__setup_cpu_e500v2 so > its done for all processors regardless of platform. How does something like this look? Let me know and I can test and submit it separately. - Nate diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index eb4b9ad..546804f 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -17,6 +17,34 @@ #include #include +_GLOBAL(__e500_icache_enable) + mfspr r3, SPRN_L1CSR1 + oris r3, r3, L1CSR1_CPE@h + ori r3, r3, (L1CSR1_ICFI | L1CSR1_ICE) + mtspr SPRN_L1CSR1, r3 /* Enable I-Cache */ + isync + blr + +_GLOBAL(__e500_dcache_enable) + msync + isync + li r3, 0 + mtspr SPRN_L1CSR0, r3 /* Disable */ + msync + isync + li r3, L1CSR0_DCFI + mtspr SPRN_L1CSR0, r3 /* Invalidate */ + msync + isync + mfspr r3, SPRN_L1CSR0 + oris r3, r3, L1CSR0_CPE@h + ori r3, r3, (L1CSR0_DCFI | L1CSR0_DCE) + msync + isync + mtspr SPRN_L1CSR0, r3 /* Enable */ + isync + blr + _GLOBAL(__setup_cpu_e200) /* enable dedicated debug exception handling resources (Debug APU) */ mfspr r3,SPRN_HID0 @@ -25,7 +53,16 @@ _GLOBAL(__setup_cpu_e200) b __setup_e200_ivors _GLOBAL(__setup_cpu_e500v1) _GLOBAL(__setup_cpu_e500v2) - b __setup_e500_ivors + mflr r4 + bl __e500_icache_enable + bl __e500_dcache_enable + bl __setup_e500_ivors + mtlr r4 + blr _GLOBAL(__setup_cpu_e500mc) - b __setup_e500mc_ivors - + mflr r4 + bl __e500_icache_enable + bl __e500_dcache_enable + bl __setup_e500mc_ivors + mtlr r4 + blr