From patchwork Mon Oct 14 14:59:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 283290 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 907022C032E for ; Tue, 15 Oct 2013 03:10:38 +1100 (EST) Received: from localhost ([::1]:37270 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VVjhl-0007qL-4f for incoming@patchwork.ozlabs.org; Mon, 14 Oct 2013 11:05:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40902) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VVjZi-0005NY-MT for qemu-devel@nongnu.org; Mon, 14 Oct 2013 10:56:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VVjZc-000222-N2 for qemu-devel@nongnu.org; Mon, 14 Oct 2013 10:56:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45698) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VVjZc-00021v-Dw for qemu-devel@nongnu.org; Mon, 14 Oct 2013 10:56:44 -0400 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r9EEufaj007100 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 14 Oct 2013 10:56:41 -0400 Received: from redhat.com (vpn1-6-139.ams2.redhat.com [10.36.6.139]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id r9EEuc3n020826; Mon, 14 Oct 2013 10:56:39 -0400 Date: Mon, 14 Oct 2013 17:59:15 +0300 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org, Anthony Liguori Message-ID: <1381762577-12526-22-git-send-email-mst@redhat.com> References: <1381762577-12526-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1381762577-12526-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: peter.maydell@linaro.org, imammedo@redhat.com, mst@redhat.com, kraxel@redhat.com, marcel.a@redhat.com Subject: [Qemu-devel] [PULL 21/43] q35: expose mmcfg size as a property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Address is already exposed, expose size for symmetry. Reviewed-by: Gerd Hoffmann Tested-by: Gerd Hoffmann Reviewed-by: Igor Mammedov Tested-by: Igor Mammedov Signed-off-by: Michael S. Tsirkin --- include/hw/pci/pcie_host.h | 1 + hw/pci-host/q35.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h index 33d75bd..acca45e 100644 --- a/include/hw/pci/pcie_host.h +++ b/include/hw/pci/pcie_host.h @@ -29,6 +29,7 @@ OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE) #define PCIE_HOST_MCFG_BASE "MCFG" +#define PCIE_HOST_MCFG_SIZE "mcfg_size" /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */ #define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index e46f286..a051b58 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -109,6 +109,16 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, visit_type_uint64(v, &w64.end, name, errp); } +static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, + void *opaque, const char *name, + Error **errp) +{ + PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); + uint32_t value = e->size; + + visit_type_uint32(v, &value, name, errp); +} + static Property mch_props[] = { DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), @@ -160,6 +170,10 @@ static void q35_host_initfn(Object *obj) q35_host_get_pci_hole64_end, NULL, NULL, NULL, NULL); + object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", + q35_host_get_mmcfg_size, + NULL, NULL, NULL, NULL); + /* Leave enough space for the biggest MCFG BAR */ /* TODO: this matches current bios behaviour, but * it's not a power of two, which means an MTRR