From patchwork Sun Oct 13 15:20:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 283098 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 99D2E2C033E for ; Mon, 14 Oct 2013 02:20:59 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 107194A07A; Sun, 13 Oct 2013 17:20:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AZUL+n+cego0; Sun, 13 Oct 2013 17:20:57 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A5F2B4A081; Sun, 13 Oct 2013 17:20:56 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F10F4A081 for ; Sun, 13 Oct 2013 17:20:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ny14d8KOW791 for ; Sun, 13 Oct 2013 17:20:44 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by theia.denx.de (Postfix) with ESMTPS id 660004A07A for ; Sun, 13 Oct 2013 17:20:38 +0200 (CEST) Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3cyRRm2sgdz3hhrv; Sun, 13 Oct 2013 17:20:36 +0200 (CEST) X-Auth-Info: 3PfU9AzyTIzaTWriBz1sMG9tslLCgk/YzoMDWXOmNyE= Received: from chi.lan (unknown [195.140.253.167]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3cyRRm0Mdlzbbkp; Sun, 13 Oct 2013 17:20:36 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Date: Sun, 13 Oct 2013 17:20:34 +0200 Message-Id: <1381677634-6589-1-git-send-email-marex@denx.de> X-Mailer: git-send-email 1.8.4.rc3 Cc: Marek Vasut , Fabio Estevam , Otavio Salvador , Hector Palacios , Tom Rini Subject: [U-Boot] [PATCH] ARM: mxs: Do not reconfigure FEC clock in FEC init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Do not reconfigure the FEC clock during board_eth_init(), otherwise the FEC might have stability issues, refuse to autonegotiate link entirely or even corrupt packets while indicating correct checksum on them. Instead, move the FEC clock init to board_early_init_f(), where all the other upstream clock are initialized and also make sure there is proper stabilization delay. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Hector Palacios Cc: Oliver Metz Cc: Otavio Salvador Cc: Stefano Babic Cc: Tom Rini Tested-by: Hector Palacios --- board/bluegiga/apx4devkit/apx4devkit.c | 10 ++++------ board/denx/m28evk/m28evk.c | 21 +++++++++++---------- board/freescale/mx28evk/mx28evk.c | 9 +++++---- board/schulercontrol/sc_sps_1/sc_sps_1.c | 19 +++++++++++-------- 4 files changed, 31 insertions(+), 28 deletions(-) NOTE: I'd like to get this into current release as it fixes a serious issue I observe here on the MX28EVK (packets being corrupted on long transfers initiated early after boot). Please test this and report back ASAP. diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c index 08e79bd..044a182 100644 --- a/board/bluegiga/apx4devkit/apx4devkit.c +++ b/board/bluegiga/apx4devkit/apx4devkit.c @@ -39,6 +39,10 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); +#ifdef CONFIG_CMD_NET + cpu_eth_init(NULL); + udelay(10000); +#endif return 0; } @@ -79,12 +83,6 @@ int board_eth_init(bd_t *bis) int ret; struct eth_device *dev; - ret = cpu_eth_init(bis); - if (ret) { - printf("FEC MXS: Unable to init FEC clocks\n"); - return ret; - } - ret = fecmxc_initialize(bis); if (ret) { printf("FEC MXS: Unable to init FEC\n"); diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index 33d38cf..5065ee8 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; */ int board_early_init_f(void) { + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + /* IO0 clock at 480MHz */ mxs_set_ioclk(MXC_IOCLK0, 480000); /* IO1 clock at 480MHz */ @@ -36,6 +39,14 @@ int board_early_init_f(void) /* SSP2 clock at 160MHz */ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); +#ifdef CONFIG_CMD_NET + cpu_eth_init(NULL); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, + CLKCTRL_ENET_TIME_SEL_RMII_CLK); + udelay(10000); +#endif + #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 | @@ -110,19 +121,9 @@ int fecmxc_mii_postcall(int phy) int board_eth_init(bd_t *bis) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; - ret = cpu_eth_init(bis); - if (ret) - return ret; - - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, - CLKCTRL_ENET_TIME_SEL_RMII_CLK); - #if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) /* Reset the new PHY */ gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0); diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index 5005fe2..2c93c44 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -41,6 +41,11 @@ int board_early_init_f(void) /* SSP2 clock at 160MHz */ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); +#ifdef CONFIG_CMD_NET + cpu_eth_init(NULL); + udelay(10000); +#endif + #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | @@ -102,10 +107,6 @@ int board_eth_init(bd_t *bis) struct eth_device *dev; int ret; - ret = cpu_eth_init(bis); - if (ret) - return ret; - /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, &clkctrl_regs->hw_clkctrl_enet); diff --git a/board/schulercontrol/sc_sps_1/sc_sps_1.c b/board/schulercontrol/sc_sps_1/sc_sps_1.c index 7f0b591..9d3c970 100644 --- a/board/schulercontrol/sc_sps_1/sc_sps_1.c +++ b/board/schulercontrol/sc_sps_1/sc_sps_1.c @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; */ int board_early_init_f(void) { + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + /* IO0 clock at 480MHz */ mxs_set_ioclk(MXC_IOCLK0, 480000); /* IO1 clock at 480MHz */ @@ -36,6 +39,14 @@ int board_early_init_f(void) /* SSP2 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK2, 96000, 0); +#ifdef CONFIG_CMD_NET + cpu_eth_init(NULL); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_TIME_SEL_MASK, + CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN); + udelay(10000); +#endif + #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 | @@ -69,16 +80,8 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; int ret; - ret = cpu_eth_init(bis); - - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_TIME_SEL_MASK, - CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN); - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); if (ret) { printf("FEC MXS: Unable to init FEC0\n");