diff mbox

serial: Fix bug of ucc_uart

Message ID 1244471076-25905-1-git-send-email-daveliu@freescale.com (mailing list archive)
State Accepted, archived
Commit b45cc9eff72e0871ffb83ae32c3dbca382909706
Delegated to: Kumar Gala
Headers show

Commit Message

Dave Liu June 8, 2009, 2:24 p.m. UTC 
Current ucc_uart driver doesn't work at UART mode,
The TxBD[READY] is not cleared by H/W (RISC engine)
when user send characters to Tx buffer of QE UART.
so, these characters stay on the QE forever, never
go to UART line.

The patch is fixing th bug.

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 drivers/serial/ucc_uart.c |   19 ++++++++++++++-----
 1 files changed, 14 insertions(+), 5 deletions(-)

Comments

Kumar Gala June 11, 2009, 3:39 a.m. UTC | #1 
On Jun 8, 2009, at 9:24 AM, Dave Liu wrote:

> Current ucc_uart driver doesn't work at UART mode,
> The TxBD[READY] is not cleared by H/W (RISC engine)
> when user send characters to Tx buffer of QE UART.
> so, these characters stay on the QE forever, never
> go to UART line.
>
> The patch is fixing th bug.
>
> Signed-off-by: Dave Liu <daveliu@freescale.com>
> ---
> drivers/serial/ucc_uart.c |   19 ++++++++++++++-----
> 1 files changed, 14 insertions(+), 5 deletions(-)

applied to next.

(Cleaned up the commit message a bit)

- k
diff mbox

Patch

diff --git a/drivers/serial/ucc_uart.c b/drivers/serial/ucc_uart.c
index 7de66c0..e945e78 100644
--- a/drivers/serial/ucc_uart.c
+++ b/drivers/serial/ucc_uart.c
@@ -681,22 +681,27 @@  static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
 	out_be16(&uccup->rccm, 0xc0ff);
 
 	/* Configure the GUMR registers for UART */
-	if (soft_uart)
+	if (soft_uart) {
 		/* Soft-UART requires a 1X multiplier for TX */
 		clrsetbits_be32(&uccp->gumr_l,
 			UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
 			UCC_SLOW_GUMR_L_RDCR_MASK,
 			UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
 			UCC_SLOW_GUMR_L_RDCR_16);
-	else
+
+		clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
+			UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
+	} else {
 		clrsetbits_be32(&uccp->gumr_l,
 			UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
 			UCC_SLOW_GUMR_L_RDCR_MASK,
 			UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
 			UCC_SLOW_GUMR_L_RDCR_16);
 
-	clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
-		UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
+		clrsetbits_be32(&uccp->gumr_h,
+			UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
+			UCC_SLOW_GUMR_H_RFW);
+	}
 
 #ifdef LOOPBACK
 	clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
@@ -706,7 +711,7 @@  static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
 		UCC_SLOW_GUMR_H_CDS);
 #endif
 
-	/* Enable rx interrupts  and clear all pending events.  */
+	/* Disable rx interrupts  and clear all pending events.  */
 	out_be16(&uccp->uccm, 0);
 	out_be16(&uccp->ucce, 0xffff);
 	out_be16(&uccp->udsr, 0x7e7e);
@@ -765,6 +770,10 @@  static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
 		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
 		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
 			QE_CR_PROTOCOL_UNSPECIFIED, 0);
+	} else {
+		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
+		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
+			QE_CR_PROTOCOL_UART, 0);
 	}
 }