diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index eb7cbbc..ceab92f 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -15,7 +15,9 @@
 #include <phy.h>
 #include <hwconfig.h>
 
-#define FSL_MAX_NUM_USB_CTRLS	2
+#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#endif
 
 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
 static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -128,7 +130,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 	char str[5];
 	int i, j;
 
-	for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) {
+	for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
 		int mode_idx = -1, phy_idx = -1;
 		snprintf(str, 5, "%s%d", "usb", i);
 		if (hwconfig(str)) {
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 946ea97..4cc12ee 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -133,6 +133,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
@@ -153,6 +154,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -162,6 +164,7 @@
 #elif defined(CONFIG_P1012)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -178,6 +181,7 @@
 #elif defined(CONFIG_P1013)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
@@ -196,6 +200,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
@@ -210,6 +215,7 @@
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
@@ -228,6 +234,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 #elif defined(CONFIG_P1021)
 #define CONFIG_MAX_CPUS			2
@@ -243,6 +250,7 @@
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
 #elif defined(CONFIG_P1022)
 #define CONFIG_MAX_CPUS			2
@@ -250,6 +258,7 @@
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -263,6 +272,7 @@
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
@@ -280,6 +290,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -289,6 +300,7 @@
 #elif defined(CONFIG_P1025)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -307,6 +319,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
@@ -326,7 +339,7 @@
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 #define CONFIG_SYS_FSL_ERRATUM_A005125
-
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
@@ -338,6 +351,7 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
@@ -381,6 +395,7 @@
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_USB14
@@ -413,6 +428,7 @@
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
@@ -460,6 +476,7 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
@@ -495,6 +512,7 @@
 #define CONFIG_SYS_NUM_FM2_DTSEC	5
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
@@ -519,6 +537,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
@@ -535,6 +554,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_DSP_DDR_ADDR	0x40000000
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR	0xc0000000
@@ -581,6 +601,7 @@
 #define CONFIG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PME_CLK		0
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
@@ -615,6 +636,7 @@
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
@@ -637,6 +659,7 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -671,6 +694,7 @@
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_PME_PLAT_CLK_DIV		2
 #define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
