From patchwork Sat Jun 6 21:12:36 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerhard Pircher X-Patchwork-Id: 28193 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 1A772B70AD for ; Sun, 7 Jun 2009 07:19:51 +1000 (EST) Received: by ozlabs.org (Postfix) id 0B7FADDDA0; Sun, 7 Jun 2009 07:19:51 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (bilbo.ozlabs.org [203.10.76.25]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "bilbo.ozlabs.org", Issuer "CAcert Class 3 Root" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 08991DDD1B for ; Sun, 7 Jun 2009 07:19:51 +1000 (EST) Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by bilbo.ozlabs.org (Postfix) with ESMTP id 962ABB734E for ; Sun, 7 Jun 2009 07:19:27 +1000 (EST) X-Greylist: delayed 398 seconds by postgrey-1.32 at bilbo; Sun, 07 Jun 2009 07:19:20 EST Received: from mail.gmx.net (mail.gmx.net [213.165.64.20]) by bilbo.ozlabs.org (Postfix) with SMTP id B1224B70AC for ; Sun, 7 Jun 2009 07:19:19 +1000 (EST) Received: (qmail 1059 invoked by uid 0); 6 Jun 2009 21:12:38 -0000 Received: from 85.127.161.6 by www093.gmx.net with HTTP; Sat, 06 Jun 2009 23:12:36 +0200 (CEST) Date: Sat, 06 Jun 2009 23:12:36 +0200 From: "Gerhard Pircher" Message-ID: <20090606211236.245370@gmx.net> MIME-Version: 1.0 Subject: [PATCH] powerpc: Enable additional BAT registers in setup_745x_specifics() To: linuxppc-dev@lists.ozlabs.org X-Authenticated: #6097454 X-Flags: 0001 X-Mailer: WWW-Mail 6100 (Global Message Exchange) X-Priority: 3 X-Provags-ID: V01U2FsdGVkX19ps9YMc3lp33X0oHe9fqCcHbnlG0UwsQ1TXTH6uC aUGJkDZLyEBP9Qen/FkRitfay7exjX/I+URQ== X-GMX-UID: k75Yar0+eSEqQk9pNnQhvTp+IGRvbwAG X-FuHaFi: 0.57 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Currently the kernel expects the additional four IBAT and DBAT registers to be available, but doesn't enable these registers on 745x CPUs, which have them disabled after reset. Thus set the HIGH_BAT_EN bit in HID0 register, if the corresponding MMU feature is defined. Signed-off-by: Gerhard Pircher --- arch/powerpc/kernel/cpu_setup_6xx.S | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S index 54f767e..1e9949e 100644 --- a/arch/powerpc/kernel/cpu_setup_6xx.S +++ b/arch/powerpc/kernel/cpu_setup_6xx.S @@ -239,6 +239,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR) ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE ori r11,r11,HID0_LRSTK | HID0_BTIC oris r11,r11,HID0_DPM@h +BEGIN_MMU_FTR_SECTION + oris r11,r11,HID0_HIGH_BAT@h +END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) BEGIN_FTR_SECTION xori r11,r11,HID0_BTIC END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)