From patchwork Wed Oct 9 10:28:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 281798 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 43BBE2C00A6 for ; Wed, 9 Oct 2013 21:29:28 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=D6ansaFbpRC5b1l6F 51FrguQtIaw4KNU+JPQeACH5x3GseskJ21lgzHyECNDzeqr+6ItAhyuxx+tuWDBs nIVRN5helWM2lrMacaYCSK+11tYGbH+3YSXwhQ8ZAvFwggjqwpN8XOyyWBC50lAS Y1IdshAzgUG4D4qomgYbLpLdUQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=vXyYxi2bakrxy1XQgxAasym 01Zs=; b=BCnFzN4Lc8RPeDKJmknk3ZZMbdVaKQ1yxfwDudO9itdrBlTP8iLb7Bi pXJXZPiXYyqgxwMJBSuefh5zCR7Sjse2vc/7lLdQqCnnxa2uCYVPWpZZTHcQlJww +tEJL7zN3qrZ6JbvbIK6YU5W9LI+miGGEHGot8mxxhL+oQ+MTI9s= Received: (qmail 17820 invoked by alias); 9 Oct 2013 10:29:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17808 invoked by uid 89); 9 Oct 2013 10:29:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pb0-f47.google.com Received: from mail-pb0-f47.google.com (HELO mail-pb0-f47.google.com) (209.85.160.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 09 Oct 2013 10:29:21 +0000 Received: by mail-pb0-f47.google.com with SMTP id rr4so701948pbb.20 for ; Wed, 09 Oct 2013 03:29:19 -0700 (PDT) X-Received: by 10.68.40.169 with SMTP id y9mr884313pbk.193.1381314559679; Wed, 09 Oct 2013 03:29:19 -0700 (PDT) Received: from msticlxl57.ims.intel.com ([192.55.54.40]) by mx.google.com with ESMTPSA id fk4sm53850431pab.23.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 09 Oct 2013 03:29:18 -0700 (PDT) Date: Wed, 9 Oct 2013 14:28:44 +0400 From: Kirill Yukhin To: Richard Henderson Cc: Uros Bizjak , Vladimir Makarov , Jakub Jelinek , GCC Patches Subject: Re: [PATCH i386 3/8] [AVX512] [12/n] Add AVX-512 patterns: V_512 and VI_512 iterators. Message-ID: <20131009102844.GK52466@msticlxl57.ims.intel.com> References: <20130808112524.GA40277@msticlxl57.ims.intel.com> <20130814072638.GD52726@msticlxl57.ims.intel.com> <52129604.6040305@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <52129604.6040305@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, > This patch is still far too large. > > I think you should split it up based on every single mode iterator that > you need to add or change. Here's 12th subpatch. It introduces VF_512 and VI_512 iterators. Is it Ok? Testing: 1. Bootstrap pass. 2. make check shows no regressions. 3. Spec 2000 & 2006 build show no regressions both with and without -mavx512f option. 4. Spec 2000 & 2006 run shows no stability regressions without -mavx512f option. --- Thanks, K PS. If it is Ok - I am going to strip out ChangeLog lines from big patch. --- gcc/config/i386/sse.md | 59 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6adcdd3..0ba1670 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -122,6 +122,9 @@ (define_mode_iterator V_256 [V32QI V16HI V8SI V4DI V8SF V4DF]) +;; All 512bit vector modes +(define_mode_iterator V_512 [V64QI V32HI V16SI V8DI V16SF V8DF]) + ;; All 256bit and 512bit vector modes (define_mode_iterator V_256_512 [V32QI V16HI V8SI V4DI V8SF V4DF @@ -337,7 +340,10 @@ ;; All 256bit vector integer modes (define_mode_iterator VI_256 [V32QI V16HI V8SI V4DI]) -;; Random 128bit vector integer mode combinations +;; All 512bit vector integer modes +(define_mode_iterator VI_512 [V64QI V32HI V16SI V8DI]) + +;; Various 128bit vector integer mode combinations (define_mode_iterator VI12_128 [V16QI V8HI]) (define_mode_iterator VI14_128 [V16QI V4SI]) (define_mode_iterator VI124_128 [V16QI V8HI V4SI]) @@ -1853,6 +1859,23 @@ (const_string "0"))) (set_attr "mode" "")]) +(define_expand "vcond" + [(set (match_operand:V_512 0 "register_operand") + (if_then_else:V_512 + (match_operator 3 "" + [(match_operand:VF_512 4 "nonimmediate_operand") + (match_operand:VF_512 5 "nonimmediate_operand")]) + (match_operand:V_512 1 "general_operand") + (match_operand:V_512 2 "general_operand")))] + "TARGET_AVX512F + && (GET_MODE_NUNITS (mode) + == GET_MODE_NUNITS (mode))" +{ + bool ok = ix86_expand_fp_vcond (operands); + gcc_assert (ok); + DONE; +}) + (define_expand "vcond" [(set (match_operand:V_256 0 "register_operand") (if_then_else:V_256 @@ -6457,6 +6480,23 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) +(define_expand "vcond" + [(set (match_operand:V_512 0 "register_operand") + (if_then_else:V_512 + (match_operator 3 "" + [(match_operand:VI_512 4 "nonimmediate_operand") + (match_operand:VI_512 5 "general_operand")]) + (match_operand:V_512 1) + (match_operand:V_512 2)))] + "TARGET_AVX512F + && (GET_MODE_NUNITS (mode) + == GET_MODE_NUNITS (mode))" +{ + bool ok = ix86_expand_int_vcond (operands); + gcc_assert (ok); + DONE; +}) + (define_expand "vcond" [(set (match_operand:V_256 0 "register_operand") (if_then_else:V_256 @@ -6506,6 +6546,23 @@ DONE; }) +(define_expand "vcondu" + [(set (match_operand:V_512 0 "register_operand") + (if_then_else:V_512 + (match_operator 3 "" + [(match_operand:VI_512 4 "nonimmediate_operand") + (match_operand:VI_512 5 "nonimmediate_operand")]) + (match_operand:V_512 1 "general_operand") + (match_operand:V_512 2 "general_operand")))] + "TARGET_AVX512F + && (GET_MODE_NUNITS (mode) + == GET_MODE_NUNITS (mode))" +{ + bool ok = ix86_expand_int_vcond (operands); + gcc_assert (ok); + DONE; +}) + (define_expand "vcondu" [(set (match_operand:V_256 0 "register_operand") (if_then_else:V_256