Patchwork Add MSI interrupts to DTS of MPC8315E-RDB

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Submitter Leon Woestenberg
Date June 5, 2009, 2:45 p.m.
Message ID <4a292f95.05a4100a.1a14.0a04@mx.google.com>
Download mbox | patch
Permalink /patch/28154/
State Superseded
Headers show

Comments

Leon Woestenberg - June 5, 2009, 2:45 p.m.
The PCIe MSI interrupts are missing from the device tree source, and
thus were not enabled. This patch adds them.

Tested to work on MPC8315E-RDB with custom FPGA PCIe device.

Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
Tested-by: Leon Woestenberg <leon@sidebranch.com>
David Gibson - June 6, 2009, 12:44 a.m.
On Fri, Jun 05, 2009 at 07:45:41AM -0700, leon.woestenberg@gmail.com wrote:
> The PCIe MSI interrupts are missing from the device tree source, and
> thus were not enabled. This patch adds them.
> 
> Tested to work on MPC8315E-RDB with custom FPGA PCIe device.
> 
> Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
> Tested-by: Leon Woestenberg <leon@sidebranch.com>
> 
> diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
> index 3f4c5fb..4f04667 100644
> --- a/arch/powerpc/boot/dts/mpc8315erdb.dts
> +++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
> @@ -322,6 +322,21 @@
>  			reg = <0x700 0x100>;
>  			device_type = "ipic";
>  		};
> +
> +		ipic-msi@7c0 {
> +			compatible = "fsl,ipic-msi";
> +                        reg = <0x7c0 0x40>;
> +                        msi-available-ranges = <0 0x100>;

This patch appears not to use consistent whitespace formatting.

Patch

diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 3f4c5fb..4f04667 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -322,6 +322,21 @@ 
 			reg = <0x700 0x100>;
 			device_type = "ipic";
 		};
+
+		ipic-msi@7c0 {
+			compatible = "fsl,ipic-msi";
+                        reg = <0x7c0 0x40>;
+                        msi-available-ranges = <0 0x100>;
+			interrupts = < 0x43 0x8
+						   0x4  0x8
+						   0x51 0x8
+						   0x52 0x8
+						   0x56 0x8
+						   0x57 0x8
+						   0x58 0x8
+						   0x59 0x8 >;
+			interrupt-parent = < &ipic >;
+		};
 	};
 
 	pci0: pci@e0008500 {