From patchwork Tue Oct 8 07:47:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 281347 X-Patchwork-Delegate: swarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 503BA2C054D for ; Tue, 8 Oct 2013 18:47:56 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754888Ab3JHHry (ORCPT ); Tue, 8 Oct 2013 03:47:54 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:2595 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754817Ab3JHHrw (ORCPT ); Tue, 8 Oct 2013 03:47:52 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 08 Oct 2013 00:47:50 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 08 Oct 2013 00:43:44 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 08 Oct 2013 00:43:44 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.327.1; Tue, 8 Oct 2013 00:47:51 -0700 From: Joseph Lo To: Stephen Warren CC: Peter De Schrijver , , , Joseph Lo Subject: [PATCH] ARM: tegra: add clock properties for devices of Tegra124 Date: Tue, 8 Oct 2013 15:47:40 +0800 Message-ID: <1381218460-23123-1-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo --- This patch was based on the series of Tegra124 clock driver and the basic support of Tegra124. It coulud be used to replace the "HACK" patch in the basic support of Tegra124 series. --- arch/arm/boot/dts/tegra124-venice2.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 16 ++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 2bfc7ab..5859ec2 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -17,4 +17,17 @@ pmc@7000e400 { nvidia,invert-interrupt; }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 905f148..7862024 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,3 +1,4 @@ +#include #include #include "skeleton.dtsi" @@ -27,6 +28,13 @@ , , ; + clocks = <&tegra_car TEGRA124_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; }; /* @@ -43,6 +51,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTA>; }; serial@70006040 { @@ -51,6 +60,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTB>; }; serial@70006200 { @@ -59,6 +69,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTC>; }; serial@70006300 { @@ -67,6 +78,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTD>; }; serial@70006400 { @@ -75,6 +87,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTE>; }; rtc@7000e000 { @@ -82,11 +95,14 @@ reg = <0x7000e000 0x100>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_RTC>; }; pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; }; cpus {