From patchwork Mon Oct 7 22:42:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 281286 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C987D2C0095 for ; Tue, 8 Oct 2013 10:11:33 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BA7C94A0AB; Tue, 8 Oct 2013 01:11:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id roxWQmtZy4jl; Tue, 8 Oct 2013 01:11:17 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 651014A0B0; Tue, 8 Oct 2013 01:10:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8DA6B4A098 for ; Tue, 8 Oct 2013 01:10:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AYSWsXQ0geYQ for ; Tue, 8 Oct 2013 01:10:19 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from mail-pd0-f174.google.com (mail-pd0-f174.google.com [209.85.192.174]) by theia.denx.de (Postfix) with ESMTPS id 210544A080 for ; Tue, 8 Oct 2013 01:10:09 +0200 (CEST) Received: by mail-pd0-f174.google.com with SMTP id y13so7774320pdi.19 for ; Mon, 07 Oct 2013 16:10:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IQm+WpKOC0FogpgfXUMTsBo8WvAu8B3wZXBokDY4IrY=; b=M+kxoSZcEFirhAnKk9OGlism9CZJEMr0M2AiKQHFIu3046jjG8hmWsGBMDWogV2bqB bTJMRXEUL+sVzBzCyApmDo5APnFicGnPrpl6U/dDlAxdUl2c8fo9vhcj3BnbFYxN0RrP Bu8N2m9idFkqcsPNBLJMzSqlnD2xSbBOOX93M0IKIUS8AF7s5sbk88ocqtVN4jmhlMI5 cSvTwSSKHH4dyI+0e/7KvbnRpABL//jze3Rs6AWTbASkqLQJK19XDCRPycljZyqYY0tb gonvCpjNJhcDKQ8+eSvcz55Z12KE7NCW2DmkFY6Ebu9BRe/5Ptnc84EOE9zWHzlLAIpZ QyXg== X-Received: by 10.68.240.2 with SMTP id vw2mr33709222pbc.80.1381187407808; Mon, 07 Oct 2013 16:10:07 -0700 (PDT) Received: from tom-ubuntu64.nvidia.com ([216.228.120.20]) by mx.google.com with ESMTPSA id yo2sm42436549pab.8.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 07 Oct 2013 16:10:07 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Mon, 7 Oct 2013 15:42:55 -0700 Message-Id: <1381185778-25722-5-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1381185778-25722-1-git-send-email-twarren@nvidia.com> References: <1381185778-25722-1-git-send-email-twarren@nvidia.com> X-NVConfidentiality: public Cc: twarren.nvidia@gmail.com, swarren@nvidia.com, jimmzhang@nvidia.com, Tom Warren , treding@nvidia.com Subject: [U-Boot] [PATCH 5/8] Tegra124: Add common CPU (shared) files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de These files are used by both SPL and main U-Boot. Change-Id: I5b762fc3f9886f588372c7706feaf80c50305c75 Signed-off-by: Tom Warren --- arch/arm/cpu/tegra-common/ap.c | 11 +++++++++-- arch/arm/cpu/tegra-common/board.c | 8 +++++++- arch/arm/cpu/tegra-common/cache.c | 38 +++++++++++++++----------------------- 3 files changed, 31 insertions(+), 26 deletions(-) diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 6fb11cb..c2c4a0b 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -27,7 +27,7 @@ int tegra_get_chip(void) /* * This is undocumented, Chip ID is bits 15:8 of the register * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for - * Tegra30, and 0x35 for T114. + * Tegra30, 0x35 for T114 and 0x40 for T124. */ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; debug("%s: CHIPID is 0x%02X\n", __func__, rev); @@ -81,7 +81,14 @@ int tegra_get_chip_sku(void) return TEGRA_SOC_T114; } break; + case CHIPID_TEGRA124: + switch (sku_id) { + } + case SKU_ID_T124_ENG: + return TEGRA_SOC_T124; + break; } + /* unknown chip/sku id */ printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", __func__, chip_id, sku_id); @@ -117,7 +124,7 @@ static u32 get_odmdata(void) * The BCT start and size are stored in the BIT in IRAM. * Read the data @ bct_start + (bct_size - 12). This works * on T20 and T30 BCTs, which are locked down. If this changes - * in new chips (T114, etc.), we can revisit this algorithm. + * in new chips (T1x4, etc.), we can revisit this algorithm. */ u32 bct_start, odmdata; diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c index d9cbda8..2c9613e 100644 --- a/arch/arm/cpu/tegra-common/board.c +++ b/arch/arm/cpu/tegra-common/board.c @@ -109,12 +109,18 @@ static int uart_configs[] = { -1, -1, -1, -#else /* Tegra114 */ +#elif defined(CONFIG_TEGRA114) -1, -1, -1, FUNCMUX_UART4_GMI, /* UARTD */ -1, +#else /* Tegra12x */ + FUNCMUX_UART1_KBC, /* UARTA */ + -1, + -1, + FUNCMUX_UART4_GPIO, /* UARTD */ + -1, #endif }; diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c index 48e9319..11fe960 100644 --- a/arch/arm/cpu/tegra-common/cache.c +++ b/arch/arm/cpu/tegra-common/cache.c @@ -1,17 +1,8 @@ /* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2013 + * NVIDIA Corporation * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * SPDX-License-Identifier: GPL-2.0+ */ /* Tegra cache routines */ @@ -33,16 +24,17 @@ void config_cache(void) "orr r0, r0, #0x41\n" "mcr p15, 0, r0, c1, c0, 1\n"); - /* Currently, only T114 needs this L2 cache change to boot Linux */ + /* Currently, only T1x4 needs this L2 cache change to boot Linux */ reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); - if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) - return; - /* - * Systems with an architectural L2 cache must not use the PL310. - * Config L2CTLR here for a data RAM latency of 3 cycles. - */ - asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); - reg &= ~7; - reg |= 2; - asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); + reg = (reg >> HIDREV_CHIPID_SHIFT) & 0xFF; + if ((reg == CHIPID_TEGRA114) || (reg == CHIPID_TEGRA124)) { + /* + * SoCs with an architectural L2 cache must not use the PL310. + * Config L2CTLR here for a data RAM latency of 3 cycles. + */ + asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); + reg &= ~7; + reg |= 2; + asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); + } }