Patchwork [12/13] Add xxspltw

login
register
mail settings
Submitter Tom Musta
Date Oct. 4, 2013, 1:26 p.m.
Message ID <524EC1ED.3040201@gmail.com>
Download mbox | patch
Permalink /patch/280616/
State New
Headers show

Comments

Tom Musta - Oct. 4, 2013, 1:26 p.m.
This patch adds the VSX Splat Word (xxsplatw) instruction.

This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   50 
++++++++++++++++++++++++++++++++++++++++++++++++
  1 files changed, 50 insertions(+), 0 deletions(-)


@@ -7364,6 +7365,54 @@ static void gen_xxsel(DisasContext * ctx)
      tcg_temp_free(c);
  }

+static void gen_xxspltw(DisasContext *ctx)
+{
+    TCGv_i64 b, b2;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+
+    b = tcg_temp_new();
+    b2 = tcg_temp_new();
+
+    tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
+
+    switch (UIM(ctx->opcode)) {
+        case 0: {
+            tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul);
+            tcg_gen_shri_i64(b, b, 32);
+            break;
+        }
+        case 1: {
+            tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_andi_i64(b, b, 0x00000000FFFFFFFFul);
+            break;
+        }
+        case 2: {
+            tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
+            tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul);
+            tcg_gen_shri_i64(b, b, 32);
+            break;
+        }
+        case 3: {
+            tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
+            tcg_gen_andi_i64(b, b, 0x00000000FFFFFFFFul);
+            break;
+        }
+    }
+
+    tcg_gen_shli_i64(b2, b, 32);
+    tcg_gen_or_i64(b, b, b2);
+
+    tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), b);
+    tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), b);
+
+    tcg_temp_free(b);
+    tcg_temp_free(b2);
+}
+

  /***                           SPE 
extension                               ***/
  /* Register moves */
@@ -9879,6 +9928,7 @@ VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
  VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
  GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
  GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),

  #define GEN_XXSEL_ROW(opc3) \
  GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
Richard Henderson - Oct. 9, 2013, 8:19 p.m.
On 10/04/2013 06:26 AM, Tom Musta wrote:
> +        case 0: {
> +            tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
> +            tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul);
> +            tcg_gen_shri_i64(b, b, 32);
> +            break;
...
> +        case 2: {
> +            tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
> +            tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul);
> +            tcg_gen_shri_i64(b, b, 32);
> +            break;

No need for the and.

Perhaps better as

   TCGv_i64 vsr = (uim & 2 ? cpu_vrsl(xb) : cpu_vrsh(xb));
   if (uim & 1) {
       tcg_gen_ext32u_i64(b, vsr);
   } else {
       tcg_gen_shri_i32(b, vsr, 32);
   }

> +    tcg_gen_shli_i64(b2, b, 32);
> +    tcg_gen_or_i64(b, b, b2);

deposit.


r~

Patch

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a29db98..5bab048 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -503,6 +503,7 @@  EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
  EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
  EXTRACT_HELPER_SPLIT(xC, 3, 1,  6, 5);
  EXTRACT_HELPER(DM, 8, 2);
+EXTRACT_HELPER(UIM, 16, 2);
  /*****************************************************************************/
  /* PowerPC instructions 
table                                                */