From patchwork Fri Oct 4 09:12:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 280564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C3F842C00DC for ; Fri, 4 Oct 2013 19:18:12 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751600Ab3JDJSL (ORCPT ); Fri, 4 Oct 2013 05:18:11 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:11278 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750982Ab3JDJSK (ORCPT ); Fri, 4 Oct 2013 05:18:10 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 04 Oct 2013 02:18:04 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 04 Oct 2013 02:18:10 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 04 Oct 2013 02:18:10 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.327.1; Fri, 4 Oct 2013 02:18:09 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 04 Oct 2013 02:18:09 -0700 Received: from tbergstrom-lnx.nvidia.com (tbergstrom-lnx.nvidia.com [10.21.24.170]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r949FrAA025096; Fri, 4 Oct 2013 02:18:06 -0700 (PDT) From: Peter De Schrijver To: Peter De Schrijver CC: Mike Turquette , Stephen Warren , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Prashant Gaikwad , Thierry Reding , Paul Walmsley , , , , Subject: [PATCH 3/5] clk: tegra124: Add common clk IDs to clk-id.h Date: Fri, 4 Oct 2013 12:12:42 +0300 Message-ID: <1380878014-22088-4-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty In-Reply-To: <1380878014-22088-1-git-send-email-pdeschrijver@nvidia.com> References: <1380878014-22088-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-id.h | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index b2a4d45..4ac3017 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -191,6 +191,33 @@ enum clk_id { tegra_clk_clk_out_3_mux, tegra_clk_dsia_mux, tegra_clk_dsib_mux, + + tegra124_clk_isp, + tegra_clk_uarte, + tegra_clk_entropy, + tegra_clk_i2c6, + tegra_clk_hdmi_audio, + tegra_clk_clk72Mhz, + tegra_clk_vic03, + tegra_clk_adx1, + tegra_clk_amx1, + tegra_clk_sor0, + tegra_clk_sata_oob, + tegra_clk_sata, + tegra_clk_vi_sensor2, + tegra_clk_ispb, + tegra_clk_vim2_clk, + tegra_clk_pcie, + tegra_clk_afi, + tegra_clk_sata_cold, + tegra_clk_dpaux, + tegra_clk_gpu, + tegra_clk_pll_p_out5, + tegra_clk_cml0, + tegra_clk_cml1, + tegra_clk_pll_c4, + tegra_clk_pll_dp, + tegra_clk_max, };