Patchwork [2/5] clk: tegra: Add periph regs bank X

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Submitter Peter De Schrijver
Date Oct. 4, 2013, 9:12 a.m.
Message ID <1380878014-22088-3-git-send-email-pdeschrijver@nvidia.com>
Download mbox | patch
Permalink /patch/280563/
State Not Applicable, archived
Headers show

Comments

Peter De Schrijver - Oct. 4, 2013, 9:12 a.m.
Tegra124 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)
Thierry Reding - Oct. 10, 2013, 10:43 a.m.
On Fri, Oct 04, 2013 at 12:12:41PM +0300, Peter De Schrijver wrote:
> Tegra124 has an extra bank of peripheral clock registers. Add it to the
> generic peripheral clock code.
> 
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/clk.c |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> index c8c84ce..0240dc3 100644
> --- a/drivers/clk/tegra/clk.c
> +++ b/drivers/clk/tegra/clk.c
> @@ -57,6 +57,8 @@
>  #define RST_DEVICES_CLR_V		0x434
>  #define RST_DEVICES_SET_W		0x438
>  #define RST_DEVICES_CLR_W		0x43c
> +#define RST_DEVICES_SET_X		0x290
> +#define RST_DEVICES_CLR_X		0x294

Perhaps sort these numerically rather than alphabetically? Also I don't
see where the CLK_OUT_ENB_X, CLK_OUT_ENB_{SET,CLR}_X or RST_DEVICES_X
registers are defined. Perhaps they were part of some other patch or a
series that this depends on?

>  
>  /* Global data of Tegra CPU CAR ops */
>  static struct tegra_cpu_car_ops dummy_car_ops;
> @@ -109,6 +111,14 @@ static struct tegra_clk_periph_regs periph_regs[] = {
>  		.rst_set_reg = RST_DEVICES_SET_W,
>  		.rst_clr_reg = RST_DEVICES_CLR_W,
>  	},
> +	[5] = {
> +		.enb_reg = CLK_OUT_ENB_X,
> +		.enb_set_reg = CLK_OUT_ENB_SET_X,
> +		.enb_clr_reg = CLK_OUT_ENB_CLR_X,
> +		.rst_reg = RST_DEVICES_X,
> +		.rst_set_reg = RST_DEVICES_SET_X,
> +		.rst_clr_reg = RST_DEVICES_CLR_X,
> +	},
>  };

Thierry
Peter De Schrijver - Oct. 10, 2013, 11 a.m.
On Thu, Oct 10, 2013 at 12:43:07PM +0200, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Fri, Oct 04, 2013 at 12:12:41PM +0300, Peter De Schrijver wrote:
> > Tegra124 has an extra bank of peripheral clock registers. Add it to the
> > generic peripheral clock code.
> > 
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > ---
> >  drivers/clk/tegra/clk.c |   10 ++++++++++
> >  1 files changed, 10 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> > index c8c84ce..0240dc3 100644
> > --- a/drivers/clk/tegra/clk.c
> > +++ b/drivers/clk/tegra/clk.c
> > @@ -57,6 +57,8 @@
> >  #define RST_DEVICES_CLR_V		0x434
> >  #define RST_DEVICES_SET_W		0x438
> >  #define RST_DEVICES_CLR_W		0x43c
> > +#define RST_DEVICES_SET_X		0x290
> > +#define RST_DEVICES_CLR_X		0x294
> 
> Perhaps sort these numerically rather than alphabetically? Also I don't

Why? I think alphabetically makes more sense or possibly per bank.

> see where the CLK_OUT_ENB_X, CLK_OUT_ENB_{SET,CLR}_X or RST_DEVICES_X
> registers are defined. Perhaps they were part of some other patch or a
> series that this depends on?
> 

Cheers,

Peter.
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Patch

diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index c8c84ce..0240dc3 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -57,6 +57,8 @@ 
 #define RST_DEVICES_CLR_V		0x434
 #define RST_DEVICES_SET_W		0x438
 #define RST_DEVICES_CLR_W		0x43c
+#define RST_DEVICES_SET_X		0x290
+#define RST_DEVICES_CLR_X		0x294
 
 /* Global data of Tegra CPU CAR ops */
 static struct tegra_cpu_car_ops dummy_car_ops;
@@ -109,6 +111,14 @@  static struct tegra_clk_periph_regs periph_regs[] = {
 		.rst_set_reg = RST_DEVICES_SET_W,
 		.rst_clr_reg = RST_DEVICES_CLR_W,
 	},
+	[5] = {
+		.enb_reg = CLK_OUT_ENB_X,
+		.enb_set_reg = CLK_OUT_ENB_SET_X,
+		.enb_clr_reg = CLK_OUT_ENB_CLR_X,
+		.rst_reg = RST_DEVICES_X,
+		.rst_set_reg = RST_DEVICES_SET_X,
+		.rst_clr_reg = RST_DEVICES_CLR_X,
+	},
 };
 
 struct tegra_clk_periph_regs * __init get_reg_bank(int clkid)