From patchwork Wed Oct 2 14:44:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 279755 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 592092C0091 for ; Thu, 3 Oct 2013 00:46:55 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 85E9E4A067; Wed, 2 Oct 2013 16:46:43 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ubzKLljhnqMT; Wed, 2 Oct 2013 16:46:43 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B700E4A080; Wed, 2 Oct 2013 16:46:24 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 85D954A080 for ; Wed, 2 Oct 2013 16:46:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id i4i7QgwbG0Zz for ; Wed, 2 Oct 2013 16:46:01 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qe0-f74.google.com (mail-qe0-f74.google.com [209.85.128.74]) by theia.denx.de (Postfix) with ESMTPS id 1E0C84A09E for ; Wed, 2 Oct 2013 16:45:38 +0200 (CEST) Received: by mail-qe0-f74.google.com with SMTP id a11so84839qen.3 for ; Wed, 02 Oct 2013 07:45:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zVepQE4G5KEiz5HgSBOgb/EW7qMcd0z++D+eeY+IZ0w=; b=U//A9J0iYUAxPln/9O5oxb7EkoVaq2tSlnzR7ueGzBVJ5ZVffLlIR65yfrzacbulpz XuOnj9csOGqX/fVzbPs3gaj6rCLDgVu0svS30T7wcDCEbSskLj8R1Ugi99i4N557cPPu Mjc3i4AhtY7NYq6KZP1sYmH3ZckJX8fMhrVoJ2rbvlCNxuaGRPLdwVPvICDIlM19dbEb g2yg1hczdDSp3JF57knpUUVkXLr+YO1oDlKjxtkXxWuLdOz8HmGio5MjG29IyoCzbH6t b5WwjN301uvd5HTMm3KuTfgylmU4bw954R/shtSEdSxJ+rJSYSDOMC4APoounxFLDN8v 0vFw== X-Gm-Message-State: ALoCoQl/sfHt+tNY0riucNvY2oKREHaOqe5P+rydRucqspzJJvI5znMVCNxaig2Luf0ZT6MIW0B1K6dc1jy6ciZurXonyFTI4hvD9E7IzX5+eTbqw1LE827X2FEydC5/Oi5z2pzMbMy5MCaBR/l7tlW+ajik44Q4qnhq4OOiWl0ONLwdBc5yx1ulTQS241q196HVSGojugFv X-Received: by 10.236.53.70 with SMTP id f46mr2203896yhc.17.1380725136455; Wed, 02 Oct 2013 07:45:36 -0700 (PDT) Received: from corp2gmr1-2.hot.corp.google.com (corp2gmr1-2.hot.corp.google.com [172.24.189.93]) by gmr-mx.google.com with ESMTPS id d23si84933yhn.2.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Wed, 02 Oct 2013 07:45:36 -0700 (PDT) Received: from kaki.bld.corp.google.com (kaki.bld.corp.google.com [172.29.216.32]) by corp2gmr1-2.hot.corp.google.com (Postfix) with ESMTP id 47B415A419C; Wed, 2 Oct 2013 07:45:36 -0700 (PDT) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 6FA3E220FAB; Wed, 2 Oct 2013 08:45:12 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 2 Oct 2013 08:44:41 -0600 Message-Id: <1380725088-20893-2-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1380725088-20893-1-git-send-email-sjg@chromium.org> References: <1380725088-20893-1-git-send-email-sjg@chromium.org> Cc: Tom Rini , u-boot-review@google.com Subject: [U-Boot] [PATCH 1/8] am33xx/omap: Allow cache enable for all Sitara/OMAP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Enable the cache for all devices, unless CONFIG_SYS_DCACHE_OFF is defined. This speeds up the Beaglebone Black boot considerable. (Tested only on Beaglebone Black with SD card boot) Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/omap-common/Makefile | 4 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 41 ------------------- arch/arm/cpu/armv7/omap-common/omap-cache.c | 56 ++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap3/board.c | 8 ---- board/siemens/common/board.c | 9 ----- 5 files changed, 60 insertions(+), 58 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/omap-cache.c diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 75b3753..3487972 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -21,6 +21,10 @@ COBJS += vc.o COBJS += abb.o endif +ifeq ($(CONFIG_SYS_DCACHE_OFF),) +COBJS += omap-cache.o +endif + ifeq ($(CONFIG_OMAP34XX),) COBJS += boot-common.o SOBJS += lowlevel_init.o diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 85d3754..74f5e45 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -18,13 +18,8 @@ #include #include #include -#include #include -#define ARMV7_DCACHE_WRITEBACK 0xe -#define ARMV7_DOMAIN_CLIENT 1 -#define ARMV7_DOMAIN_MASK (0x3 << 0) - DECLARE_GLOBAL_DATA_PTR; void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) @@ -264,39 +259,3 @@ int print_cpuinfo(void) return 0; } -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} - -void dram_bank_mmu_setup(int bank) -{ - bd_t *bd = gd->bd; - int i; - - u32 start = bd->bi_dram[bank].start >> 20; - u32 size = bd->bi_dram[bank].size >> 20; - u32 end = start + size; - - debug("%s: bank: %d\n", __func__, bank); - for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); - -} - -void arm_init_domains(void) -{ - u32 reg; - - reg = get_dacr(); - /* - * Set DOMAIN to client access so that all permissions - * set in pagetables are validated by the mmu. - */ - reg &= ~ARMV7_DOMAIN_MASK; - reg |= ARMV7_DOMAIN_CLIENT; - set_dacr(reg); -} -#endif diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c new file mode 100644 index 0000000..579bebf --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -0,0 +1,56 @@ +/* + * + * Common functions for OMAP4/5 based boards + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Author : + * Aneesh V + * Steve Sakoman + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7d1f8d9..fd12cdc 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -478,11 +478,3 @@ void omap3_outer_cache_disable(void) omap3_update_aux_cr(0, 0x2); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 6279c32..c3c7f2d 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -159,13 +159,4 @@ U_BOOT_CMD( "Sends U-Boot into infinite loop", "" ); - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - printf("Enable d-cache\n"); - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* CONFIG_SYS_DCACHE_OFF */ #endif /* !CONFIG_SPL_BUILD */