From patchwork Wed Oct 2 05:12:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Macke X-Patchwork-Id: 279675 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B45442C00B1 for ; Wed, 2 Oct 2013 19:55:52 +1000 (EST) Received: from localhost ([::1]:35060 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VRJ9q-0007hd-1S for incoming@patchwork.ozlabs.org; Wed, 02 Oct 2013 05:55:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56758) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VREjd-0002Hu-Do for qemu-devel@nongnu.org; Wed, 02 Oct 2013 01:12:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VREjX-0004LD-LP for qemu-devel@nongnu.org; Wed, 02 Oct 2013 01:12:29 -0400 Received: from www11.your-server.de ([213.133.104.11]:43173) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VREjX-0004Kk-Et for qemu-devel@nongnu.org; Wed, 02 Oct 2013 01:12:23 -0400 Received: from [24.84.34.12] (helo=[192.168.0.16]) by www11.your-server.de with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.74) (envelope-from ) id 1VREjQ-00058t-Pi; Wed, 02 Oct 2013 07:12:17 +0200 Message-ID: <524BAB2A.4050202@macke.de> Date: Tue, 01 Oct 2013 22:12:10 -0700 From: Sebastian Macke User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 MIME-Version: 1.0 To: qemu-devel@nongnu.org X-Authenticated-Sender: sebastian@macke.de X-Virus-Scanned: Clear (ClamAV 0.97.6/17924/Wed Oct 2 00:46:00 2013) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 213.133.104.11 X-Mailman-Approved-At: Wed, 02 Oct 2013 05:54:51 -0400 Cc: openrisc@lists.openrisc.net, openrisc@lists.opencores.org Subject: [Qemu-devel] [PATCH] Correction of the TLB handling of the OpenRISC target X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hi, this patch corrects two problems for the OpenRISC Target in QEMU. The first one corrects one obvious bug concerning the handling of page faults while reading from a page. The second part removes a non-conforming behavior for the first page of the memory. I have tested this patch with the newest Linux kernel and compared the output with or1ksim. Sebastian From 4491bae7109e2b4de5a8de8a7e4b08d1f19ac70e Mon Sep 17 00:00:00 2001 From: Sebastian Macke Date: Tue, 1 Oct 2013 21:39:38 -0700 Subject: [PATCH] Correction of the TLB handling of the OpenRISC target This patch correct two problems. The first one corrects one obvious bug concerning the handling of page faults while reading from a page. The second part removes a non-conforming behavior for the first page of the memory. I have tested this patch with the newest Linux kernel and compared the output with or1ksim. Signed-off-by: Sebastian Macke Reviewed-by: Jia Liu --- target-openrisc/mmu.c | 9 +-------- 1 files changed, 1 insertions(+), 8 deletions(-) diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index 57f5616..22d7cbe 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -102,7 +102,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, } } - if ((rw & 0) && ((right & PAGE_READ) == 0)) { + if (!(rw & 1) && ((right & PAGE_READ) == 0)) { return TLBRET_BADADDR; } if ((rw & 1) && ((right & PAGE_WRITE) == 0)) { @@ -122,13 +122,6 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, { int ret = TLBRET_MATCH; - /* [0x0000--0x2000]: unmapped */ - if (address < 0x2000 && (cpu->env.sr & SR_SM)) { - *physical = address; - *prot = PAGE_READ | PAGE_WRITE; - return ret; - } - if (rw == 2) { /* ITLB */ *physical = 0; ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical,