From patchwork Tue Oct 1 21:27:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 279603 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 19E3C2C00B1 for ; Wed, 2 Oct 2013 07:40:25 +1000 (EST) Received: from localhost ([::1]:32978 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VR7g7-0005FN-7k for incoming@patchwork.ozlabs.org; Tue, 01 Oct 2013 17:40:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52370) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VR7RR-0004nv-D0 for qemu-devel@nongnu.org; Tue, 01 Oct 2013 17:25:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VR7RK-0004JY-SF for qemu-devel@nongnu.org; Tue, 01 Oct 2013 17:25:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38398) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VR7RK-0004IT-G4 for qemu-devel@nongnu.org; Tue, 01 Oct 2013 17:25:06 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r91LP3N2000318 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 1 Oct 2013 17:25:04 -0400 Received: from redhat.com (vpn1-4-190.ams2.redhat.com [10.36.4.190]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id r91LP0mW020213; Tue, 1 Oct 2013 17:25:01 -0400 Date: Wed, 2 Oct 2013 00:27:25 +0300 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <1380662727-24170-23-git-send-email-mst@redhat.com> References: <1380662727-24170-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1380662727-24170-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: pbonzini@redhat.com, afaerber@suse.de, Anthony Liguori , kraxel@redhat.com Subject: [Qemu-devel] [PATCH v7 22/27] ich9: APIs for pc guest info X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This adds APIs that will be used to fill in acpi tables, implemented using QOM, to various ich9 components. Some information is still missing in QOM, so we fall back on lookups by type instead. Reviewed-by: Gerd Hoffmann Tested-by: Gerd Hoffmann Signed-off-by: Michael S. Tsirkin --- include/hw/acpi/ich9.h | 2 ++ include/hw/i386/ich9.h | 2 ++ include/hw/pci-host/q35.h | 2 ++ hw/acpi/ich9.c | 24 ++++++++++++++++++++++++ hw/isa/lpc_ich9.c | 40 ++++++++++++++++++++++++++++++++++++++++ hw/pci-host/q35.c | 10 ++++++++++ 6 files changed, 80 insertions(+) diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index b1fe71f..82fcf9f 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -49,4 +49,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base); extern const VMStateDescription vmstate_ich9_pm; +void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp); + #endif /* HW_ACPI_ICH9_H */ diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index c5f637b..4a68b35 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -66,6 +66,8 @@ typedef struct ICH9LPCState { qemu_irq *ioapic; } ICH9LPCState; +Object *ich9_lpc_find(void); + #define Q35_MASK(bit, ms_bit, ls_bit) \ ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 6eb7ab6..f9db770 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -156,4 +156,6 @@ typedef struct Q35PCIHost { #define MCH_PCIE_DEV 1 #define MCH_PCIE_FUNC 0 +uint64_t mch_mcfg_base(void); + #endif /* HW_Q35_H */ diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 3fb443d..7e0429e 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -24,6 +24,7 @@ * GNU GPL, version 2 or (at your option) any later version. */ #include "hw/hw.h" +#include "qapi/visitor.h" #include "hw/i386/pc.h" #include "hw/pci/pci.h" #include "qemu/timer.h" @@ -228,3 +229,26 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, pm->powerdown_notifier.notify = pm_powerdown_req; qemu_register_powerdown_notifier(&pm->powerdown_notifier); } + +static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, + void *opaque, const char *name, + Error **errp) +{ + ICH9LPCPMRegs *pm = opaque; + uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; + + visit_type_uint32(v, &value, name, errp); +} + +void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp) +{ + static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN; + + object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE, + &pm->pm_io_base, errp); + object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32", + ich9_pm_get_gpe0_blk, + NULL, NULL, pm, NULL); + object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN, + &gpe0_len, errp); +} diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 5633d08..19b2198 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -29,6 +29,7 @@ */ #include "qemu-common.h" #include "hw/hw.h" +#include "qapi/visitor.h" #include "qemu/range.h" #include "hw/isa/isa.h" #include "hw/sysbus.h" @@ -525,6 +526,43 @@ static const MemoryRegionOps ich9_rst_cnt_ops = { .endianness = DEVICE_LITTLE_ENDIAN }; +Object *ich9_lpc_find(void) +{ + bool ambig; + Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig); + + if (ambig) { + return NULL; + } + return o; +} + +static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, + void *opaque, const char *name, + Error **errp) +{ + ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); + uint32_t value = ich9_lpc_sci_irq(lpc); + + visit_type_uint32(v, &value, name, errp); +} + +static void ich9_lpc_add_properties(ICH9LPCState *lpc) +{ + static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; + static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; + + object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32", + ich9_lpc_get_sci_int, + NULL, NULL, NULL, NULL); + object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, + &acpi_enable_cmd, NULL); + object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, + &acpi_disable_cmd, NULL); + + ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL); +} + static int ich9_lpc_initfn(PCIDevice *d) { ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); @@ -552,6 +590,8 @@ static int ich9_lpc_initfn(PCIDevice *d) ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 1); + ich9_lpc_add_properties(lpc); + return 0; } diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index a051b58..50063f8 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -389,6 +389,16 @@ static int mch_init(PCIDevice *d) return 0; } +uint64_t mch_mcfg_base(void) +{ + bool ambiguous; + Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); + if (!o) { + return 0; + } + return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; +} + static void mch_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);