diff mbox

[U-Boot,v3,2/2] Tegra114: Do not program CPCON field for PLLX

Message ID 1380639885-11556-2-git-send-email-treding@nvidia.com
State Accepted
Delegated to: Tom Warren
Headers show

Commit Message

Thierry Reding Oct. 1, 2013, 3:04 p.m. UTC 
PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- don't leak PLLX_BASE bits into PLLX_MISC

Changes in v2:
- new patch

 arch/arm/cpu/arm720t/tegra-common/cpu.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
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Patch

diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index aa1e04f..72c69b9 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -135,6 +135,7 @@  void adjust_pllp_out_freqs(void)
 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 		u32 divp, u32 cpcon)
 {
+	int chip = tegra_get_chip();
 	u32 reg;
 
 	/* If PLLX is already enabled, just return */
@@ -151,7 +152,10 @@  int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 	writel(reg, &pll->pll_base);
 
 	/* Set cpcon to PLLX_MISC */
-	reg = (cpcon << PLL_CPCON_SHIFT);
+	if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
+		reg = (cpcon << PLL_CPCON_SHIFT);
+	else
+		reg = 0;
 
 	/* Set dccon to PLLX_MISC if freq > 600MHz */
 	if (divn > 600)