From patchwork Tue Oct 1 07:42:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kugan Vivekanandarajah X-Patchwork-Id: 279355 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AFC9B2C00C5 for ; Tue, 1 Oct 2013 17:43:08 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=QWPxY7NIOrSTSgFauLRiRIhYdTZYSA0iGNF87C+qoHZ WYRE075wp1aonjoBjzzSIz4/ga00C503RXeGa16ZBmBk4RfuPTgRz8MzF9FCe7Gt UtaCiMd8m0fdKm8gLxJ1p44wM0iIfexR05zgg4AKtOWeCZ5Zd75Dpuau5KV2fvEo = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=h/HUugKjWZfe8v+fRlS9iHcnPE8=; b=LzMfH3J7MxYGPNbwp Xo8exv4oHBoJVawaicOBM7DwHIxlnJ8WvrksaDNC84YdM5EmUg/xWR/Zr0bTZSff M6q5ouILH92smpdvHh5iR/jfo/xs9sJizSLDM7vJSNce1HaWUBtRjTgweU0Vbq5+ nRtzX7fjXajnKKKgvs2SwtzELY= Received: (qmail 19321 invoked by alias); 1 Oct 2013 07:43:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19312 invoked by uid 89); 1 Oct 2013 07:43:02 -0000 Received: from mail-pb0-f50.google.com (HELO mail-pb0-f50.google.com) (209.85.160.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 01 Oct 2013 07:43:02 +0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.1 required=5.0 tests=ALL_TRUSTED, AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: mail-pb0-f50.google.com Received: by mail-pb0-f50.google.com with SMTP id uo5so6728738pbc.37 for ; Tue, 01 Oct 2013 00:42:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:message-id:date:from:user-agent:mime-version:to :cc:subject:content-type; bh=JS1vSPM+X+yvGBQN2QdisIDGKTKE9Td39D3Hoo1kZNs=; b=WCt39iuPb9v/l3G6HQ4ZEH/m77G0J8nwsbcJdQjOZiNbhxV7ZjQpX9vLZ/w6cY8MQS mXKbhzP8W16EWJpiD74X+lCBKlenDIqmjiRc70RbY2+PeeV69Xm1/dbRbrfe8VWEyOVo 6qrUbjxpf3C1ZRMn7HkZcIOgKuEc8b8zji5gltiI1GHldR8mfYIeIt/13mVxHf27RQfQ 8kDC7iMUGww/VCHgMubH3fGXZ0YZetIezckcRacktojRLfL/Sg+hdcqFFBD+Q9JYg6wQ EeCLGw0nwvBuvl4zjtb0nKq8WRCg1zuPeufV9twsvvYMwABXnKImABQkI47xT4La42oZ uo8A== X-Gm-Message-State: ALoCoQn3nroNudse74YJtPonPzbMxdjpPJ5ki92NsIA6FSv8jUqnKEujDsvS3IXrD2bPeVW8JkWJ X-Received: by 10.68.244.130 with SMTP id xg2mr28130127pbc.13.1380613378252; Tue, 01 Oct 2013 00:42:58 -0700 (PDT) Received: from [192.168.1.3] (27-33-114-215.tpgi.com.au. [27.33.114.215]) by mx.google.com with ESMTPSA id y5sm5159291pbs.18.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Oct 2013 00:42:56 -0700 (PDT) Message-ID: <524A7CF9.5030707@linaro.org> Date: Tue, 01 Oct 2013 17:12:49 +0930 From: Kugan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [ARM, PR58578] Split shift di patterns X-IsSubscribed: yes Hi, I am attaching a patch that reverts Split shift di patterns (r197527) as it introduced PR58578. I am also attaching a patch to add a testcase based on this failiures. No regression on qemu for arm-none-eabi and new testcase now passes. Is this OK? Thanks, Kugan diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3b22081..4b9f991 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-10-01 Kugan Vivekanandarajah + + PR Target/58578 + * gcc.target/arm/pr58578.c: New test. + 2013-09-30 Jakub Jelinek PR middle-end/58564 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b094cff..e8d5464 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3867,26 +3867,13 @@ " ) -(define_insn_and_split "arm_ashldi3_1bit" +(define_insn "arm_ashldi3_1bit" [(set (match_operand:DI 0 "s_register_operand" "=r,&r") (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") (const_int 1))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "#" ; "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" - "&& reload_completed" - [(parallel [(set (reg:CC CC_REGNUM) - (compare:CC (ashift:SI (match_dup 1) (const_int 1)) - (const_int 0))) - (set (match_dup 0) (ashift:SI (match_dup 1) (const_int 1)))]) - (set (match_dup 2) (plus:SI (plus:SI (match_dup 3) (match_dup 3)) - (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] - { - operands[2] = gen_highpart (SImode, operands[0]); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[1] = gen_lowpart (SImode, operands[1]); - } + "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" [(set_attr "conds" "clob") (set_attr "length" "8") (set_attr "type" "multiple")] @@ -3964,43 +3951,18 @@ " ) -(define_insn_and_split "arm_ashrdi3_1bit" +(define_insn "arm_ashrdi3_1bit" [(set (match_operand:DI 0 "s_register_operand" "=r,&r") (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") (const_int 1))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "#" ; "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" - "&& reload_completed" - [(parallel [(set (reg:CC CC_REGNUM) - (compare:CC (ashiftrt:SI (match_dup 3) (const_int 1)) - (const_int 0))) - (set (match_dup 2) (ashiftrt:SI (match_dup 3) (const_int 1)))]) - (set (match_dup 0) (unspec:SI [(match_dup 1) - (reg:CC_C CC_REGNUM)] - UNSPEC_RRX))] - { - operands[2] = gen_highpart (SImode, operands[0]); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[1] = gen_lowpart (SImode, operands[1]); - } + "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" [(set_attr "conds" "clob") (set_attr "length" "8") (set_attr "type" "multiple")] ) -(define_insn "*rrx" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (unspec:SI [(match_operand:SI 1 "s_register_operand" "r") - (reg:CC_C CC_REGNUM)] - UNSPEC_RRX))] - "TARGET_32BIT" - "mov\\t%0, %1, rrx" - [(set_attr "conds" "use") - (set_attr "type" "mov_shift")] -) - (define_expand "ashrsi3" [(set (match_operand:SI 0 "s_register_operand" "") (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") @@ -4070,27 +4032,13 @@ " ) -(define_insn_and_split "arm_lshrdi3_1bit" +(define_insn "arm_lshrdi3_1bit" [(set (match_operand:DI 0 "s_register_operand" "=r,&r") (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") (const_int 1))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "#" ; "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" - "&& reload_completed" - [(parallel [(set (reg:CC CC_REGNUM) - (compare:CC (lshiftrt:SI (match_dup 3) (const_int 1)) - (const_int 0))) - (set (match_dup 2) (lshiftrt:SI (match_dup 3) (const_int 1)))]) - (set (match_dup 0) (unspec:SI [(match_dup 1) - (reg:CC_C CC_REGNUM)] - UNSPEC_RRX))] - { - operands[2] = gen_highpart (SImode, operands[0]); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[1] = gen_lowpart (SImode, operands[1]); - } + "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" [(set_attr "conds" "clob") (set_attr "length" "8") (set_attr "type" "multiple")] @@ -4183,21 +4131,6 @@ (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_imm,alu_shift_reg")] ) -(define_insn "*shiftsi3_compare" - [(set (reg:CC CC_REGNUM) - (compare:CC (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "arm_rhs_operand" "M,r")]) - (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") - (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] - "TARGET_32BIT" - "* return arm_output_shift(operands, 1);" - [(set_attr "conds" "set") - (set_attr "shift" "1") - (set_attr "type" "alus_shift_imm,alus_shift_reg")] -) - (define_insn "*shiftsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (match_operator:SI 3 "shift_operator" diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index c43a6a6..508603c 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -83,8 +83,6 @@ ; FPSCR rounding mode and signal inexactness. UNSPEC_VRINTA ; Represent a float to integral float rounding ; towards nearest, ties away from zero. - UNSPEC_RRX ; Rotate Right with Extend shifts register right - ; by one place, with Carry flag shifted into bit[31]. ]) (define_c_enum "unspec" [ diff --git a/gcc/testsuite/gcc.target/arm/pr58578.c b/gcc/testsuite/gcc.target/arm/pr58578.c new file mode 100644 index 0000000..2b474f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr58578.c @@ -0,0 +1,54 @@ + +/* PR target/58578 */ +/* { dg-do run } */ +/* { dg-options "-O1" } */ + +#include + +typedef struct { + long _prec; + int _flag; + long _exp; +} __my_st_t; + +typedef __my_st_t *__my_st_ptr; + +int +_test_fn (__my_st_ptr y, const __my_st_ptr xt) +{ + int inexact; + if (xt->_exp != -2147483647L) + { + (y->_flag = xt->_flag); + } + + do { + __my_st_ptr _y = y; + long _err1 = -2 * xt->_exp; + long _err2 = 2; + if (0 < _err1) + { + unsigned long _err = (unsigned long) _err1 + _err2; + if (__builtin_expect(!!(_err > _y->_prec + 1), 0)) + return 2; + return 3; + } + } while (0); + + return 0; +} + +int main () +{ + __my_st_t x, y; + long pz; + int inex; + + x._prec = 914; + y._exp = 18; + if (_test_fn (&x, &y)) + { + abort(); + } + return 0; +} diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7c9a6c5..abc545f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2013-10-01 Kugan Vivekanandarajah + + PR target/58578 + Revert + 2013-04-05 Greta Yorsh + * config/arm/arm.md (arm_ashldi3_1bit): define_insn into + define_insn_and_split. + (arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise. + (shiftsi3_compare): New pattern. + (rrx): New pattern. + * config/arm/unspecs.md (UNSPEC_RRX): New. + 2013-09-30 Richard Sandiford * vec.h (vec_prefix, vec): Prefix member names with "m_".