@@ -91,9 +91,10 @@ void set_mux_conf_regs(void)
{
/* Set MMC pins */
enable_mmc1_pin_mux();
-
/* Set Ethernet pins */
enable_enet_pin_mux();
+ /* Set NAND pins */
+ enable_nand_pin_mux();
}
void sdram_init(void)
@@ -113,6 +114,7 @@ void sdram_init(void)
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
return 0;
}
@@ -4,5 +4,6 @@
void enable_uart0_pin_mux(void);
void enable_mmc1_pin_mux(void);
void enable_enet_pin_mux(void);
+void enable_nand_pin_mux(void);
#endif /* _EVM_H */
@@ -70,6 +70,35 @@ static struct module_pin_mux enet_pin_mux[] = {
{OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */
};
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_x16_pin_mux[] = {
+ {OFFSET(pincntl89) , MODE(1) | PULL_DISABLE}, /* GPMC_AD0 */
+ {OFFSET(pincntl90) , MODE(1) | PULL_DISABLE}, /* GPMC_AD1 */
+ {OFFSET(pincntl91) , MODE(1) | PULL_DISABLE}, /* GPMC_AD2 */
+ {OFFSET(pincntl92) , MODE(1) | PULL_DISABLE}, /* GPMC_AD3 */
+ {OFFSET(pincntl93) , MODE(1) | PULL_DISABLE}, /* GPMC_AD4 */
+ {OFFSET(pincntl94) , MODE(1) | PULL_DISABLE}, /* GPMC_AD5 */
+ {OFFSET(pincntl95) , MODE(1) | PULL_DISABLE}, /* GPMC_AD6 */
+ {OFFSET(pincntl96) , MODE(1) | PULL_DISABLE}, /* GPMC_AD7 */
+ {OFFSET(pincntl97) , MODE(1) | PULL_DISABLE}, /* GPMC_AD8 */
+ {OFFSET(pincntl98) , MODE(1) | PULL_DISABLE}, /* GPMC_AD9 */
+ {OFFSET(pincntl99) , MODE(1) | PULL_DISABLE}, /* GPMC_AD10 */
+ {OFFSET(pincntl100), MODE(1) | PULL_DISABLE}, /* GPMC_AD11 */
+ {OFFSET(pincntl101), MODE(1) | PULL_DISABLE}, /* GPMC_AD12 */
+ {OFFSET(pincntl102), MODE(1) | PULL_DISABLE}, /* GPMC_AD13 */
+ {OFFSET(pincntl103), MODE(1) | PULL_DISABLE}, /* GPMC_AD14 */
+ {OFFSET(pincntl104), MODE(1) | PULL_DISABLE}, /* GPMC_AD15 */
+ {OFFSET(pincntl122), MODE(1) | PULLUP_EN}, /* GPMC_CS0 */
+ {OFFSET(pincntl128), MODE(1) | PULLDOWN_EN}, /* GPMC_ALE_ADV */
+ {OFFSET(pincntl129), MODE(1) | PULLUP_EN}, /* GPMC_OE_RE */
+ {OFFSET(pincntl130), MODE(1) | PULLUP_EN}, /* GPMC_WEN */
+ {OFFSET(pincntl131), MODE(1) | PULLDOWN_EN}, /* GPMC_BE_CLE */
+ {OFFSET(pincntl133), MODE(1) | PULLUP_EN}, /* GPMC_WAIT0 */
+ /* GPMC_WPN is controlled by Switch SW11(3) on board */
+ {-1},
+};
+#endif
+
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
@@ -84,3 +113,8 @@ void enable_enet_pin_mux(void)
{
configure_module_pin_mux(enet_pin_mux);
}
+
+void enable_nand_pin_mux(void)
+{
+ configure_module_pin_mux(nand_x16_pin_mux);
+}
@@ -18,8 +18,8 @@
#define CONFIG_TI81XX
#define CONFIG_TI814X
-#define CONFIG_SYS_NO_FLASH
#define CONFIG_OMAP
+#define CONFIG_NAND
#define CONFIG_OMAP_COMMON
#include <asm/arch/omap.h>
@@ -42,10 +42,32 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_VERSION_VARIABLE
-
#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandsrcaddr=0x280000\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
+ "bootm ${loadaddr}\0" \
+ "nandimgsize=0x500000\0"
+#else
+#define NANDARGS ""
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x80F80000\0" \
@@ -196,8 +218,6 @@
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-#define CONFIG_SPL_BOARD_INIT
-
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
@@ -207,7 +227,9 @@
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-
+/* defines required in SPL for loading U-BOOT image */
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_UBOOT_SIZE 0x240000
/*
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
@@ -239,4 +261,63 @@
#define CONFIG_PHY_ET1011C
#define CONFIG_PHY_ET1011C_TX_CLK_FIX
+/* NAND support */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_DEVICE_WIDTH 16
+#define CONFIG_SYS_NAND_BLOCK_SIZE 131072
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME 6
+/* generic driver configurations */
+#define CONFIG_NAND_OMAP_GPMC /* required for building nand driver */
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#define CONFIG_SYS_NAND_BASE 0x08000000 /* physical address to */
+ /* access nand at CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max NAND devices allowed */
+#define CONFIG_CMD_NAND
+/* SPL specific configurations */
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH /* enable ELM support */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+/* falcon mode specific configs */
+#ifdef CONFIG_SPL_OS_BOOT
+ #define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* env offset */
+ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 /* kernel offset */
+ #define CONFIG_CMD_SPL_WRITE_SIZE 0x1000
+#endif
+/* framework specific configurations */
+#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
+ #define CONFIG_MTD_DEVICE /* Required for mtdparts */
+ #define CONFIG_CMD_MTDPARTS
+ #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+ #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
+ "128k(SPL.backup1)," \
+ "128k(SPL.backup2)," \
+ "128k(SPL.backup3),1792k(u-boot)," \
+ "128k(u-boot-spl-os)," \
+ "128k(u-boot-env),5m(kernel),-(rootfs)"
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
+#undef CONFIG_ENV_IS_NOWHERE /* undef this as env is in NAND */
+#endif /* CONFIG_NAND */
+
#endif /* ! __CONFIG_TI814X_EVM_H */
ti814x_evm has on-board socket for using Micron (MT29Fxx) family of NAND devices to GPMC interface. This patch - adds NAND related pin-mux configuration for same - adds #defines for NAND partitions to TI814x configs - enables support for NAND in TI814x configs Signed-off-by: Pekon Gupta <pekon@ti.com> --- board/ti/ti814x/evm.c | 4 +- board/ti/ti814x/evm.h | 1 + board/ti/ti814x/mux.c | 34 +++++++++++++++++ include/configs/ti814x_evm.h | 91 +++++++++++++++++++++++++++++++++++++++++--- 4 files changed, 124 insertions(+), 6 deletions(-)