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Mon, 30 Sep 2013 19:59:56 +0900 (KST) X-AuditID: cbfee690-b7f3b6d000007a15-a7-524959ac5912 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 23.09.09055.CA959425; Mon, 30 Sep 2013 19:59:56 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MTX00J44QJN8020@mmp1.samsung.com>; Mon, 30 Sep 2013 19:59:56 +0900 (KST) From: Ajay Kumar To: u-boot@lists.denx.de, mk7.kang@samsung.com, dh09.lee@samsung.com Date: Mon, 30 Sep 2013 16:50:52 +0530 Message-id: <1380540055-469-4-git-send-email-ajaykumar.rs@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1380540055-469-1-git-send-email-ajaykumar.rs@samsung.com> References: <1380540055-469-1-git-send-email-ajaykumar.rs@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRmVeSWpSXmKPExsWyRsSkSndNpGeQwYx7shbXz9tZTLo/gcWi 40gLo8XPSXNYLd7u7WR3YPWYOHEdo8fZOzsYPfq2rGIMYI7isklJzcksSy3St0vgyvgz4Sd7 wQaFimeLJ7M2MM6U6mLk5JAQMJFYf+EeE4QtJnHh3nq2LkYuDiGBpYwSB/buZ4EpWnzqPwtE YhGjxN23x5ghnNlMEq9mPWMGqWIT0JbYNv0mWIeIgIvEmpk9jCA2s4CmxIfX98BqhAViJJbc /MoKYrMIqEq0nNsMVsMr4CYx4f8FdohtihLdzyawgdicAu4SS6aeA4sLAdV8nzSHEWSxhMB/ NokNU94xQgwSkPg2+RDQYg6ghKzEpgPMEHMkJQ6uuMEygVF4ASPDKkbR1ILkguKk9CITveLE 3OLSvHS95PzcTYzAAD7979mEHYz3DlgfYkwGGjeRWUo0OR8YAXkl8YbGZkYWpiamxkbmlmak CSuJ86q3WAcKCaQnlqRmp6YWpBbFF5XmpBYfYmTi4JRqYEy/IqV8bcHS1YwpgVPszCUXx9nL pNpv9RfiCbhnObny65wF5uLuDnzlF1bkfL2W9Sx06ZHnfrbmpqbu/2YZuYXvk7do79NRP7KQ ++n3WdvW3UspDn0lG+rAYxutd+3ClHaV42FZV101YrNXHF/gceqx9bbfL95sautM93vw7IhO +bQE1jvfSpRYijMSDbWYi4oTAbWhfTt2AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAIsWRmVeSWpSXmKPExsVy+t9jAd01kZ5BBs37RS2un7ezmHR/AotF x5EWRoufk+awWrzd28nuwOoxceI6Ro+zd3YwevRtWcUYwBzVwGiTkZqYklqkkJqXnJ+SmZdu q+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA7RTSaEsMacUKBSQWFyspG+HaUJoiJuu BUxjhK5vSBBcj5EBGkhYw5jxZ8JP9oINChXPFk9mbWCcKdXFyMkhIWAisfjUfxYIW0ziwr31 bF2MXBxCAosYJe6+PcYM4cxmkng16xkzSBWbgLbEtuk3wTpEBFwk1szsYQSxmQU0JT68vgdW IywQI7Hk5ldWEJtFQFWi5dxmsBpeATeJCf8vsENsU5TofjaBDcTmFHCXWDL1HFhcCKjm+6Q5 jBMYeRcwMqxiFE0tSC4oTkrPNdQrTswtLs1L10vOz93ECI6PZ1I7GFc2WBxiFOBgVOLhnbDc I0iINbGsuDL3EKMEB7OSCO8EN88gId6UxMqq1KL8+KLSnNTiQ4zJQFdNZJYSTc4Hxm5eSbyh sYm5qbGppYmFiZklacJK4rwHWq0DhQTSE0tSs1NTC1KLYLYwcXBKNTDumy/Ofu+AXH7iB74m v5cXYqdMy9qx89bLByEyu7e/tji4We8zc9PeA3HbbiV7nMv8Pbfl3bH/UkFL736ICjvwdArv xvN6kx+xr6vQMXUpCi98O+HnpYRnEzuXBhpMCr39P2UHY7hFZ6jjtQ6fr4ty7647e+SA6rT1 OX4HVT8LS780+WeuO3XrZCWW4oxEQy3mouJEALRKVgTTAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: inki.dae@samsung.com, sjg@chomium.org Subject: [U-Boot] [PATCH 3/6] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: Ajay Kumar Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock.c | 74 +++++++++++++++++++++++++++++-- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/include/asm/arch-exynos/clk.h | 1 + 3 files changed, 73 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index bc06995..e953ddc 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) * VPLL_CON: MIDV [24:16] * BPLL_CON: MIDV [25:16]: Exynos5 */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) + if (pllreg == APLL || pllreg == MPLL || + pllreg == BPLL || pllreg == SPLL) mask = 0x3ff; else mask = 0x1ff; @@ -388,6 +389,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg) r = readl(&clk->rpll_con0); k = readl(&clk->rpll_con1); break; + case SPLL: + r = readl(&clk->spll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -1035,6 +1039,40 @@ static unsigned long exynos5_get_lcd_clk(void) return pclk; } +static unsigned long exynos5420_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + sel = readl(&clk->src_disp10); + sel &= (1 << 4); + + if (sel) + sclk = get_pll_clk(SPLL); + else + sclk = get_pll_clk(RPLL); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10); + ratio = ratio & 0xf; + + pclk = sclk / (ratio + 1); + + return pclk; +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1159,6 +1197,33 @@ void exynos5_set_lcd_clk(void) writel(cfg, &clk->div_disp1_0); } +void exynos5420_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + cfg = readl(&clk->src_disp10); + cfg &= ~(0x1 << 4); + cfg |= (0 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + cfg = readl(&clk->div_disp10); + cfg &= ~(0xf << 0); + cfg |= (0 << 0); + writel(cfg, &clk->div_disp10); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1628,14 +1693,17 @@ unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); - else - return exynos5_get_lcd_clk(); + else if (proid_is_exynos5420()) + return exynos5420_get_lcd_clk(); + return exynos5_get_lcd_clk(); } void set_lcd_clk(void) { if (cpu_is_exynos4()) exynos4_set_lcd_clk(); + else if (proid_is_exynos5420()) + exynos5420_set_lcd_clk(); else exynos5_set_lcd_clk(); } diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 8e05a00..70b1c04 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -780,7 +780,7 @@ #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 #define CLK_SRC_TOP4_VAL 0x11110111 -#define CLK_SRC_TOP5_VAL 0x11111100 +#define CLK_SRC_TOP5_VAL 0x11111101 #define CLK_SRC_TOP6_VAL 0x11110111 #define CLK_SRC_TOP7_VAL 0x00022200 diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index abce246..f0b4d70 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -15,6 +15,7 @@ #define VPLL 4 #define BPLL 5 #define RPLL 6 +#define SPLL 7 enum pll_src_bit { EXYNOS_SRC_MPLL = 6,