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Mon, 30 Sep 2013 19:59:55 +0900 (KST) X-AuditID: cbfee691-b7f4a6d0000074fc-d7-524959abc3b5 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 41.66.05832.BA959425; Mon, 30 Sep 2013 19:59:55 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MTX00J44QJN8020@mmp1.samsung.com>; Mon, 30 Sep 2013 19:59:55 +0900 (KST) From: Ajay Kumar To: u-boot@lists.denx.de, mk7.kang@samsung.com, dh09.lee@samsung.com Date: Mon, 30 Sep 2013 16:50:51 +0530 Message-id: <1380540055-469-3-git-send-email-ajaykumar.rs@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1380540055-469-1-git-send-email-ajaykumar.rs@samsung.com> References: <1380540055-469-1-git-send-email-ajaykumar.rs@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRmVeSWpSXmKPExsWyRsSkTnd1pGeQwcKPEhbXz9tZTLo/gcWi 40gLo8XPSXNYLd7u7WR3YPWYOHEdo8fZOzsYPfq2rGIMYI7isklJzcksSy3St0vgypi4vY2l YL5gxZsX29kbGC/wdTFyckgImEhc2b2WHcIWk7hwbz1bFyMXh5DAUkaJ9ln32WCKfvzpY4VI LGKUOLz9DzuEM5tJ4tW7DmaQKjYBbYlt02+ygNgiAi4Sa2b2MILYzAKaEh9e3wOrERawlPj0 5ShQnIODRUBVYuqRZJAwr4CbxMbjE6CuUJTofjYBbDGngLvEkqnnwOJCQDXfJ81hhKj5zybR vVIZxGYREJD4NvkQC8hICQFZiU0HmCFKJCUOrrjBMoFReAEjwypG0dSC5ILipPQiU73ixNzi 0rx0veT83E2MwOA9/e/ZxB2M9w9YH2JMBho3kVlKNDkfGPx5JfGGxmZGFqYmpsZG5pZmpAkr ifOqt1gHCgmkJ5akZqemFqQWxReV5qQWH2Jk4uCUamB0/3n+5va2ZrZ5T69ettr9aeVZOX+u wKv2txRzVYSyGqKlbvH1fe83vK1mq3mtef2DisMnNLYfeVJw5GTlrKbtaS6MllOzrfbPtt45 1/BagMkibkfxda9DnyT7nCqbNnndqc+xG5xEkuI3bf1fb9F365Ja6GThDw4ebAH6ZRUGD47z 1ge8mvtKiaU4I9FQi7moOBEA8gaetnQCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsVy+t9jAd3VkZ5BBs/X8FtcP29nMen+BBaL jiMtjBY/J81htXi7t5PdgdVj4sR1jB5n7+xg9OjbsooxgDmqgdEmIzUxJbVIITUvOT8lMy/d Vsk7ON453tTMwFDX0NLCXEkhLzE31VbJxSdA1y0zB2inkkJZYk4pUCggsbhYSd8O04TQEDdd C5jGCF3fkCC4HiMDNJCwhjFj4vY2loL5ghVvXmxnb2C8wNfFyMkhIWAi8eNPHyuELSZx4d56 ti5GLg4hgUWMEoe3/2GHcGYzSbx618EMUsUmoC2xbfpNFhBbRMBFYs3MHkYQm1lAU+LD63tg NcIClhKfvhwFinNwsAioSkw9kgwS5hVwk9h4fAI7xDJFie5nE9hAbE4Bd4klU8+BxYWAar5P msM4gZF3ASPDKkbR1ILkguKk9FwjveLE3OLSvHS95PzcTYzg6HgmvYNxVYPFIUYBDkYlHl6L pR5BQqyJZcWVuYcYJTiYlUR4J7h5BgnxpiRWVqUW5ccXleakFh9iTAY6aiKzlGhyPjBy80ri DY1NzE2NTS1NLEzMLEkTVhLnPdhqHSgkkJ5YkpqdmlqQWgSzhYmDU6qBcbX24S+LPx1mX7Xe bO+5qH9/3k33eag1Sd7nv759Q51F8YIXzq/eOP9/tvXkev/zG+wEWC0/l/O8LK/9lj2Bc90S pX0Sl/5liin2CggkvH2u6Xzo7bMJXBv1Az6J9StOX8b22EjBiv3LtO8PetsuBnDLJ9h6ii9a nLrv3u76+AQ1Zs9c6yznHiWW4oxEQy3mouJEAGt3VeXSAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: inki.dae@samsung.com, sjg@chomium.org Subject: [U-Boot] [PATCH 2/6] arm: exynos: Add RPLL for Exynos5420 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de RPLL is needed to drive the LCD panel on Exynos5420 based boards. Signed-off-by: Ajay Kumar Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock_init.h | 3 +++ arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index a875d0b..fce502f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -75,6 +75,9 @@ struct mem_timings { unsigned spll_mdiv; unsigned spll_pdiv; unsigned spll_sdiv; + unsigned rpll_mdiv; + unsigned rpll_pdiv; + unsigned rpll_sdiv; unsigned pclk_cdrex_ratio; unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index e7f1496..c91c4a1 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, + /* RPLL @266MHz */ + .rpll_mdiv = 0x10A, + .rpll_pdiv = 0x3, + .rpll_sdiv = 0x3, .direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70, @@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void) writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock); writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock); + writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock); setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK); @@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void) while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) ; + /* Set RPLL */ + writel(RPLL_CON2_VAL, &clk->rpll_con2); + writel(RPLL_CON1_VAL, &clk->rpll_con1); + val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv); + writel(val, &clk->rpll_con0); + while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0) + ; + writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);