Patchwork [SPARC] Add peephole for memory barriers

login
register
mail settings
Submitter Eric Botcazou
Date Sept. 29, 2013, 5:53 p.m.
Message ID <6772809.aAVQ9SQRDg@polaris>
Download mbox | patch
Permalink /patch/278879/
State New
Headers show

Comments

Eric Botcazou - Sept. 29, 2013, 5:53 p.m.
This is a bit gross, but this prevents consecutive memory barriers from being 
generated, for example on accesses to atomic objects in Ada.

Tested on SPARC/Solaris, applied on the mainline.


2013-09-29  Eric Botcazou  <ebotcazou@adacore.com>

	* config/sparc/sync.md: Add peephole for consecutive memory barriers.

Patch

Index: config/sparc/sync.md
===================================================================
--- config/sparc/sync.md	(revision 202912)
+++ config/sparc/sync.md	(working copy)
@@ -93,6 +93,18 @@  (define_insn "*membar"
   "membar\t%1"
   [(set_attr "type" "multi")])
 
+(define_peephole2
+  [(set (match_operand:BLK 0 "" "")
+	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
+		    UNSPEC_MEMBAR))
+   (set (match_operand:BLK 2 "" "")
+	(unspec:BLK [(match_dup 2) (match_operand:SI 3 "const_int_operand")]
+		    UNSPEC_MEMBAR))]
+  ""
+  [(set (match_operand:BLK 0 "" "")
+	(unspec:BLK [(match_dup 0) (match_dup 1)] UNSPEC_MEMBAR))]
+{ operands[1] = GEN_INT (UINTVAL (operands[1]) | UINTVAL (operands[3])); })
+
 (define_expand "atomic_load<mode>"
   [(match_operand:I 0 "register_operand" "")
    (match_operand:I 1 "memory_operand" "")