Patchwork [U-Boot,10/10,V4] DWMMC: SMDK5420: Disable SMU for eMMC

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Submitter Rajeshwari Birje
Date Sept. 27, 2013, 12:10 p.m.
Message ID <1380283855-8070-11-git-send-email-rajeshwari.s@samsung.com>
Download mbox | patch
Permalink /patch/278563/
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Comments

Rajeshwari Birje - Sept. 27, 2013, 12:10 p.m.
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support booting via eMMC.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
Changes in V3:
	- New patch.
Changes in V4:
	Added flag to dissble SMU
 drivers/mmc/dw_mmc.c        | 10 ++++++++++
 drivers/mmc/exynos_dw_mmc.c |  3 +++
 include/dwmmc.h             | 15 +++++++++++++++
 3 files changed, 28 insertions(+)
Simon Glass - Oct. 8, 2013, 5:43 p.m.
On Fri, Sep 27, 2013 at 6:10 AM, Rajeshwari S Shinde <
rajeshwari.s@samsung.com> wrote:

> SMDK5420 has a new Security Management Unit added
> for dwmmc driver, hence, configuring the control
> registers to support booting via eMMC.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>

Acked-by: Simon Glass <sjg@chromium.org>
Jaehoon Chung - Oct. 15, 2013, 9:48 a.m.
Hi 

On 09/27/2013 09:10 PM, Rajeshwari S Shinde wrote:
> SMDK5420 has a new Security Management Unit added
> for dwmmc driver, hence, configuring the control
> registers to support booting via eMMC.
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> Changes in V3:
> 	- New patch.
> Changes in V4:
> 	Added flag to dissble SMU
>  drivers/mmc/dw_mmc.c        | 10 ++++++++++
>  drivers/mmc/exynos_dw_mmc.c |  3 +++
>  include/dwmmc.h             | 15 +++++++++++++++
>  3 files changed, 28 insertions(+)
> 
> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> index a82ee17..2a8da5c 100644
> --- a/drivers/mmc/dw_mmc.c
> +++ b/drivers/mmc/dw_mmc.c
> @@ -300,6 +300,16 @@ static int dwmci_init(struct mmc *mmc)
>  	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
>  	u32 fifo_size;
>  
> +	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
> +		dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
> +		dwmci_writel(host, EMMCP_SEND0, 0);
> +		dwmci_writel(host, EMMCP_CTRL0,
> +			     MPSCTRL_SECURE_READ_BIT |
> +			     MPSCTRL_SECURE_WRITE_BIT |
> +			     MPSCTRL_NON_SECURE_READ_BIT |
> +			     MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
> +	}
> +
>  	dwmci_writel(host, DWMCI_PWREN, 1);
>  
>  	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
> index 4ef9fec..f7439a0 100644
> --- a/drivers/mmc/exynos_dw_mmc.c
> +++ b/drivers/mmc/exynos_dw_mmc.c
> @@ -62,6 +62,9 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
>  	host->name = "EXYNOS DWMMC";
>  	host->ioaddr = (void *)regbase;
>  	host->buswidth = bus_width;
> +#ifdef CONFIG_EXYNOS5420
> +	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
> +#endif
>  
>  	if (clksel) {
>  		host->clksel_val = clksel;
> diff --git a/include/dwmmc.h b/include/dwmmc.h
> index 08ced0b..00bceec 100644
> --- a/include/dwmmc.h
> +++ b/include/dwmmc.h
> @@ -49,6 +49,9 @@
>  #define DWMCI_DSCADDR		0x094
>  #define DWMCI_BUFADDR		0x098
>  #define DWMCI_DATA		0x200
> +#define EMMCP_MPSBEGIN0		0x1200
> +#define EMMCP_SEND0		0x1204
> +#define EMMCP_CTRL0		0x120C
>  
>  /* Interrupt Mask register */
>  #define DWMCI_INTMSK_ALL	0xffffffff
> @@ -123,6 +126,18 @@
>  #define DWMCI_BMOD_IDMAC_FB	(1 << 1)
>  #define DWMCI_BMOD_IDMAC_EN	(1 << 7)
>  
> +#define MPSCTRL_SECURE_READ_BIT		(0x1<<7)
> +#define MPSCTRL_SECURE_WRITE_BIT	(0x1<<6)
> +#define MPSCTRL_NON_SECURE_READ_BIT	(0x1<<5)
> +#define MPSCTRL_NON_SECURE_WRITE_BIT	(0x1<<4)
> +#define MPSCTRL_USE_FUSE_KEY		(0x1<<3)
> +#define MPSCTRL_ECB_MODE		(0x1<<2)
> +#define MPSCTRL_ENCRYPTION		(0x1<<1)
> +#define MPSCTRL_VALID			(0x1<<0)
> +
> +/* quirks */
> +#define DWMCI_QUIRK_DISABLE_SMU		(1 << 0)

These values are exynos5420 specifi, isn't?
Then i don't want to include into "dwmmc.h"

Best Regards,
Jaehoon Chung
> +
>  struct dwmci_host {
>  	char *name;
>  	void *ioaddr;
>
Rajeshwari Birje - Oct. 15, 2013, 11:27 a.m.
Hi Jaehoon

Thank you for comments,

On Tue, Oct 15, 2013 at 3:18 PM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi
>
> On 09/27/2013 09:10 PM, Rajeshwari S Shinde wrote:
>> SMDK5420 has a new Security Management Unit added
>> for dwmmc driver, hence, configuring the control
>> registers to support booting via eMMC.
>>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> ---
>> Changes in V3:
>>       - New patch.
>> Changes in V4:
>>       Added flag to dissble SMU
>>  drivers/mmc/dw_mmc.c        | 10 ++++++++++
>>  drivers/mmc/exynos_dw_mmc.c |  3 +++
>>  include/dwmmc.h             | 15 +++++++++++++++
>>  3 files changed, 28 insertions(+)
>>
>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
>> index a82ee17..2a8da5c 100644
>> --- a/drivers/mmc/dw_mmc.c
>> +++ b/drivers/mmc/dw_mmc.c
>> @@ -300,6 +300,16 @@ static int dwmci_init(struct mmc *mmc)
>>       struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
>>       u32 fifo_size;
>>
>> +     if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
>> +             dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
>> +             dwmci_writel(host, EMMCP_SEND0, 0);
>> +             dwmci_writel(host, EMMCP_CTRL0,
>> +                          MPSCTRL_SECURE_READ_BIT |
>> +                          MPSCTRL_SECURE_WRITE_BIT |
>> +                          MPSCTRL_NON_SECURE_READ_BIT |
>> +                          MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
>> +     }
>> +
Is this ok?
or do you want me to create a function pointer for same and define the
function for this in exynos_dwmmc.c and call it here?

>>       dwmci_writel(host, DWMCI_PWREN, 1);
>>
>>       if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>> index 4ef9fec..f7439a0 100644
>> --- a/drivers/mmc/exynos_dw_mmc.c
>> +++ b/drivers/mmc/exynos_dw_mmc.c
>> @@ -62,6 +62,9 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
>>       host->name = "EXYNOS DWMMC";
>>       host->ioaddr = (void *)regbase;
>>       host->buswidth = bus_width;
>> +#ifdef CONFIG_EXYNOS5420
>> +     host->quirks = DWMCI_QUIRK_DISABLE_SMU;
>> +#endif
>>
>>       if (clksel) {
>>               host->clksel_val = clksel;
>> diff --git a/include/dwmmc.h b/include/dwmmc.h
>> index 08ced0b..00bceec 100644
>> --- a/include/dwmmc.h
>> +++ b/include/dwmmc.h
>> @@ -49,6 +49,9 @@
>>  #define DWMCI_DSCADDR                0x094
>>  #define DWMCI_BUFADDR                0x098
>>  #define DWMCI_DATA           0x200
>> +#define EMMCP_MPSBEGIN0              0x1200
>> +#define EMMCP_SEND0          0x1204
>> +#define EMMCP_CTRL0          0x120C
>>
>>  /* Interrupt Mask register */
>>  #define DWMCI_INTMSK_ALL     0xffffffff
>> @@ -123,6 +126,18 @@
>>  #define DWMCI_BMOD_IDMAC_FB  (1 << 1)
>>  #define DWMCI_BMOD_IDMAC_EN  (1 << 7)
>>
>> +#define MPSCTRL_SECURE_READ_BIT              (0x1<<7)
>> +#define MPSCTRL_SECURE_WRITE_BIT     (0x1<<6)
>> +#define MPSCTRL_NON_SECURE_READ_BIT  (0x1<<5)
>> +#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
>> +#define MPSCTRL_USE_FUSE_KEY         (0x1<<3)
>> +#define MPSCTRL_ECB_MODE             (0x1<<2)
>> +#define MPSCTRL_ENCRYPTION           (0x1<<1)
>> +#define MPSCTRL_VALID                        (0x1<<0)
>> +
>> +/* quirks */
>> +#define DWMCI_QUIRK_DISABLE_SMU              (1 << 0)
>
> These values are exynos5420 specifi, isn't?
> Then i don't want to include into "dwmmc.h"
Fine will move this to arch/arm/include/asm/arch-exynos/dwmmc.h
>
> Best Regards,
> Jaehoon Chung
>> +

Patch

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index a82ee17..2a8da5c 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -300,6 +300,16 @@  static int dwmci_init(struct mmc *mmc)
 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 	u32 fifo_size;
 
+	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+		dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
+		dwmci_writel(host, EMMCP_SEND0, 0);
+		dwmci_writel(host, EMMCP_CTRL0,
+			     MPSCTRL_SECURE_READ_BIT |
+			     MPSCTRL_SECURE_WRITE_BIT |
+			     MPSCTRL_NON_SECURE_READ_BIT |
+			     MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
+	}
+
 	dwmci_writel(host, DWMCI_PWREN, 1);
 
 	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 4ef9fec..f7439a0 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -62,6 +62,9 @@  int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
 	host->name = "EXYNOS DWMMC";
 	host->ioaddr = (void *)regbase;
 	host->buswidth = bus_width;
+#ifdef CONFIG_EXYNOS5420
+	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
+#endif
 
 	if (clksel) {
 		host->clksel_val = clksel;
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 08ced0b..00bceec 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -49,6 +49,9 @@ 
 #define DWMCI_DSCADDR		0x094
 #define DWMCI_BUFADDR		0x098
 #define DWMCI_DATA		0x200
+#define EMMCP_MPSBEGIN0		0x1200
+#define EMMCP_SEND0		0x1204
+#define EMMCP_CTRL0		0x120C
 
 /* Interrupt Mask register */
 #define DWMCI_INTMSK_ALL	0xffffffff
@@ -123,6 +126,18 @@ 
 #define DWMCI_BMOD_IDMAC_FB	(1 << 1)
 #define DWMCI_BMOD_IDMAC_EN	(1 << 7)
 
+#define MPSCTRL_SECURE_READ_BIT		(0x1<<7)
+#define MPSCTRL_SECURE_WRITE_BIT	(0x1<<6)
+#define MPSCTRL_NON_SECURE_READ_BIT	(0x1<<5)
+#define MPSCTRL_NON_SECURE_WRITE_BIT	(0x1<<4)
+#define MPSCTRL_USE_FUSE_KEY		(0x1<<3)
+#define MPSCTRL_ECB_MODE		(0x1<<2)
+#define MPSCTRL_ENCRYPTION		(0x1<<1)
+#define MPSCTRL_VALID			(0x1<<0)
+
+/* quirks */
+#define DWMCI_QUIRK_DISABLE_SMU		(1 << 0)
+
 struct dwmci_host {
 	char *name;
 	void *ioaddr;