@@ -2334,6 +2334,50 @@ static void handle_fpdp3s32(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_tmp);
}
+static void handle_fpdp3s64(DisasContext *s, uint32_t insn)
+{
+ int rd = get_bits(insn, 0, 5);
+ int rn = get_bits(insn, 5, 5);
+ int ra = get_bits(insn, 10, 5);
+ int rm = get_bits(insn, 16, 5);
+ bool is_neg = get_bits(insn, 21, 1);
+ bool is_sub = get_bits(insn, 15, 1);
+ int freg_offs_n = offsetof(CPUARMState, vfp.regs[rn * 2]);
+ int freg_offs_a = offsetof(CPUARMState, vfp.regs[ra * 2]);
+ int freg_offs_m = offsetof(CPUARMState, vfp.regs[rm * 2]);
+ int freg_offs_d = offsetof(CPUARMState, vfp.regs[rd * 2]);
+ TCGv_i64 tcg_op1 = tcg_temp_new_i64();
+ TCGv_i64 tcg_op2 = tcg_temp_new_i64();
+ TCGv_i64 tcg_op3 = tcg_temp_new_i64();
+ TCGv_i64 tcg_res = tcg_temp_new_i64();
+ TCGv_ptr fpst = get_fpstatus_ptr();
+
+ tcg_gen_ld_i64(tcg_op1, cpu_env, freg_offs_n);
+ tcg_gen_ld_i64(tcg_op2, cpu_env, freg_offs_m);
+ tcg_gen_ld_i64(tcg_op3, cpu_env, freg_offs_a);
+
+ if (is_neg) {
+ gen_helper_vfp_negd(tcg_op1, tcg_op1);
+ gen_helper_vfp_negd(tcg_op3, tcg_op3);
+ }
+
+ gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
+ if (is_sub) {
+ gen_helper_vfp_subd(tcg_res, tcg_op3, tcg_res, fpst);
+ } else {
+ gen_helper_vfp_addd(tcg_res, tcg_op3, tcg_res, fpst);
+ }
+
+ clear_fpreg(rd);
+ tcg_gen_st_i64(tcg_res, cpu_env, freg_offs_d);
+
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i64(tcg_op1);
+ tcg_temp_free_i64(tcg_op2);
+ tcg_temp_free_i64(tcg_op3);
+ tcg_temp_free_i64(tcg_res);
+}
+
/* SIMD ORR */
static void handle_simdorr(DisasContext *s, uint32_t insn)
{
@@ -2979,6 +3023,8 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
case 0x1f:
if (!get_bits(insn, 29, 3) && !get_bits(insn, 22, 2)) {
handle_fpdp3s32(s, insn);
+ } else if (!get_bits(insn, 29, 3) && (get_bits(insn, 22, 2) == 0x1)) {
+ handle_fpdp3s64(s, insn);
} else {
unallocated_encoding(s);
}
This patch adds emulation for the "Floating-point data-processing (3 source)" group of instructions in their 64 bit flavors. Signed-off-by: Alexander Graf <agraf@suse.de> --- target-arm/translate-a64.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)