@@ -2234,6 +2234,55 @@ static void handle_fpdp2s32(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_tmp);
}
+/* Floating-point data-processing (2 source) - 64 bit */
+static void handle_fpdp2s64(DisasContext *s, uint32_t insn)
+{
+ int rd = get_bits(insn, 0, 5);
+ int rn = get_bits(insn, 5, 5);
+ int rm = get_bits(insn, 16, 5);
+ int opcode = get_bits(insn, 12, 4);
+ int freg_offs_n = offsetof(CPUARMState, vfp.regs[rn * 2]);
+ int freg_offs_m = offsetof(CPUARMState, vfp.regs[rm * 2]);
+ int freg_offs_d = offsetof(CPUARMState, vfp.regs[rd * 2]);
+ TCGv_i64 tcg_op1 = tcg_temp_new_i64();
+ TCGv_i64 tcg_op2 = tcg_temp_new_i64();
+ TCGv_i64 tcg_res = tcg_temp_new_i64();
+ TCGv_ptr fpst = get_fpstatus_ptr();
+
+ tcg_gen_ld_i64(tcg_op1, cpu_env, freg_offs_n);
+ tcg_gen_ld_i64(tcg_op2, cpu_env, freg_offs_m);
+
+ switch (opcode) {
+ case 0x0: /* FMUL */
+ gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x8: /* FNMUL */
+ gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
+ gen_helper_vfp_negd(tcg_res, tcg_res);
+ break;
+ case 0x1: /* FDIV */
+ gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x2: /* FADD */
+ gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x3: /* FSUB */
+ gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ default:
+ unallocated_encoding(s);
+ return;
+ }
+
+ clear_fpreg(rd);
+ tcg_gen_st_i64(tcg_res, cpu_env, freg_offs_d);
+
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i64(tcg_op1);
+ tcg_temp_free_i64(tcg_op2);
+ tcg_temp_free_i64(tcg_res);
+}
+
/* SIMD ORR */
static void handle_simdorr(DisasContext *s, uint32_t insn)
{
@@ -2834,6 +2883,9 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
} else if (!get_bits(insn, 29, 3) && !get_bits(insn, 22, 2) &&
get_bits(insn, 21, 1) && (get_bits(insn, 10, 2) == 0x2)) {
handle_fpdp2s32(s, insn);
+ } else if (!get_bits(insn, 29, 3) && (get_bits(insn, 22, 2) == 0x1) &&
+ get_bits(insn, 21, 1) && (get_bits(insn, 10, 2) == 0x2)) {
+ handle_fpdp2s64(s, insn);
} else {
unallocated_encoding(s);
}
This patch adds emulation for the "Floating-point data-processing (2 source)" group of instructions in their 64 bit flavors. Signed-off-by: Alexander Graf <agraf@suse.de> --- target-arm/translate-a64.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)