diff mbox

[46/60] AArch64: Add rev instruction family emulation

Message ID 1380242934-20953-47-git-send-email-agraf@suse.de
State New
Headers show

Commit Message

Alexander Graf Sept. 27, 2013, 12:48 a.m. UTC 
This patch adds emlulation support for rev and rbit instructions.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-arm/helper-a64.c    | 19 +++++++++++++++++++
 target-arm/helper-a64.h    |  1 +
 target-arm/translate-a64.c | 38 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+)

Comments

Richard Henderson Sept. 27, 2013, 9:07 p.m. UTC | #1 
On 09/26/2013 05:48 PM, Alexander Graf wrote:
> This patch adds emlulation support for rev and rbit instructions.
> 
> Signed-off-by: Alexander Graf <agraf@suse.de>
> ---
>  target-arm/helper-a64.c    | 19 +++++++++++++++++++
>  target-arm/helper-a64.h    |  1 +
>  target-arm/translate-a64.c | 38 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 58 insertions(+)
> 
> diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
> index a56ce75..e20b89f 100644
> --- a/target-arm/helper-a64.c
> +++ b/target-arm/helper-a64.c
> @@ -237,3 +237,22 @@ int64_t HELPER(sdiv64)(int64_t num, int64_t den)
>        return LLONG_MIN;
>      return num / den;
>  }
> +
> +uint64_t HELPER(rbit64)(uint64_t x)
> +{
> +    x =  ((x & 0xff00000000000000ULL) >> 56)
> +       | ((x & 0x00ff000000000000ULL) >> 40)
> +       | ((x & 0x0000ff0000000000ULL) >> 24)
> +       | ((x & 0x000000ff00000000ULL) >> 8)
> +       | ((x & 0x00000000ff000000ULL) << 8)
> +       | ((x & 0x0000000000ff0000ULL) << 24)
> +       | ((x & 0x000000000000ff00ULL) << 40)
> +       | ((x & 0x00000000000000ffULL) << 56);

This first step is of course bswap64, no?

> +    case 0x0: /* RBIT */
> +        if (is_32bit) {
> +            tcg_tmp = tcg_temp_new_i32();
> +            tcg_gen_trunc_i64_i32(tcg_tmp, cpu_reg(rn));
> +            gen_helper_rbit(tcg_tmp, tcg_tmp);
> +            tcg_gen_extu_i32_i64(cpu_reg(rd), tcg_tmp);
> +            tcg_temp_free_i32(tcg_tmp);
> +        } else {
> +            gen_helper_rbit64(cpu_reg(rd), cpu_reg(rn));
> +        }

I suppose that works.  Alternately, compute as

    rd = rbit64(rn << 32);

> +    case 0x1: /* REV16 */
> +        tcg_gen_bswap16_i64(cpu_reg(rd), cpu_reg(rn));
> +        break;
> +    case 0x2: /* REV32 */
> +        tcg_gen_bswap32_i64(cpu_reg(rd), cpu_reg(rn));
> +        break;

Aren't these two wrong?  Doesn't revN swap pairs of N bits
all the way up the register?  See gen_rev16 for A32.

Certainly one could use bswap32_i64 for REV32 if is_32bit.


r~
diff mbox

Patch

diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index a56ce75..e20b89f 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -237,3 +237,22 @@  int64_t HELPER(sdiv64)(int64_t num, int64_t den)
       return LLONG_MIN;
     return num / den;
 }
+
+uint64_t HELPER(rbit64)(uint64_t x)
+{
+    x =  ((x & 0xff00000000000000ULL) >> 56)
+       | ((x & 0x00ff000000000000ULL) >> 40)
+       | ((x & 0x0000ff0000000000ULL) >> 24)
+       | ((x & 0x000000ff00000000ULL) >> 8)
+       | ((x & 0x00000000ff000000ULL) << 8)
+       | ((x & 0x0000000000ff0000ULL) << 24)
+       | ((x & 0x000000000000ff00ULL) << 40)
+       | ((x & 0x00000000000000ffULL) << 56);
+    x =  ((x & 0xf0f0f0f0f0f0f0f0ULL) >> 4)
+       | ((x & 0x0f0f0f0f0f0f0f0fULL) << 4);
+    x =  ((x & 0x8888888888888888ULL) >> 3)
+       | ((x & 0x4444444444444444ULL) >> 1)
+       | ((x & 0x2222222222222222ULL) << 1)
+       | ((x & 0x1111111111111111ULL) << 3);
+    return x;
+}
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h
index ad1a94a..5e5cda0 100644
--- a/target-arm/helper-a64.h
+++ b/target-arm/helper-a64.h
@@ -26,3 +26,4 @@  DEF_HELPER_FLAGS_2(cond, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_4(cinc, TCG_CALL_NO_RWG_SE, i64, i32, i32, i64, i64)
 DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
+DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 6e0f4bd..208d06b 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1566,6 +1566,42 @@  static void handle_shift_reg(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_shifted);
 }
 
+static void handle_rev(DisasContext *s, uint32_t insn)
+{
+    int rd = get_reg(insn);
+    int rn = get_bits(insn, 5, 5);
+    int opc = get_bits(insn, 10, 2);
+    bool is_32bit = !get_bits(insn, 31, 1);
+    TCGv_i32 tcg_tmp;
+
+    switch (opc) {
+    case 0x0: /* RBIT */
+        if (is_32bit) {
+            tcg_tmp = tcg_temp_new_i32();
+            tcg_gen_trunc_i64_i32(tcg_tmp, cpu_reg(rn));
+            gen_helper_rbit(tcg_tmp, tcg_tmp);
+            tcg_gen_extu_i32_i64(cpu_reg(rd), tcg_tmp);
+            tcg_temp_free_i32(tcg_tmp);
+        } else {
+            gen_helper_rbit64(cpu_reg(rd), cpu_reg(rn));
+        }
+        break;
+    case 0x1: /* REV16 */
+        tcg_gen_bswap16_i64(cpu_reg(rd), cpu_reg(rn));
+        break;
+    case 0x2: /* REV32 */
+        tcg_gen_bswap32_i64(cpu_reg(rd), cpu_reg(rn));
+        break;
+    case 0x3: /* REV64 */
+        tcg_gen_bswap64_i64(cpu_reg(rd), cpu_reg(rn));
+        break;
+    }
+
+    if (is_32bit) {
+        tcg_gen_ext32u_i64(cpu_reg(rd), cpu_reg(rd));
+    }
+}
+
 /* SIMD ORR */
 static void handle_simdorr(DisasContext *s, uint32_t insn)
 {
@@ -2132,6 +2168,8 @@  void disas_a64_insn(CPUARMState *env, DisasContext *s)
             handle_div(s, insn);
         } else if ((insn & 0x7fe0f000) == 0x1ac02000) {
             handle_shift_reg(s, insn);
+        } else if ((insn & 0x7ffff000) == 0x5ac00000) {
+            handle_rev(s, insn);
         } else {
             unallocated_encoding(s);
         }