| Message ID | 20130926205137.GA28417@ibm-tiger.the-meissners.org |
|---|---|
| State | New |
| Headers | show |
Just to be clear, I was only asking about the change in rs6000.c. The other two changes (rs6000-builtins.def, rs6000.h) will be part of the next patch set.
On Thu, Sep 26, 2013 at 4:51 PM, Michael Meissner <meissner@linux.vnet.ibm.com> wrote: > I discovered that I was setting the wv/wu constraints incorrectly to > ALTIVEC_REGS, which leads to reload failures in some cases. > > Is this patch ok to apply along with the previous patch assuming it bootstraps > and has no regressions with make check? It builds the programs that had > failures with the previous patch. > > 2013-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> > > * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Don't > allow wv/wu constraints to be ALTIVEC_REGISTERS unless DF/SF can > occupy the Altivec registers. Okay. Can you add a testcase to catch this in the future? Thanks, David
On Thu, Sep 26, 2013 at 06:56:37PM -0400, David Edelsohn wrote: > On Thu, Sep 26, 2013 at 4:51 PM, Michael Meissner > <meissner@linux.vnet.ibm.com> wrote: > > I discovered that I was setting the wv/wu constraints incorrectly to > > ALTIVEC_REGS, which leads to reload failures in some cases. > > > > Is this patch ok to apply along with the previous patch assuming it bootstraps > > and has no regressions with make check? It builds the programs that had > > failures with the previous patch. > > > > 2013-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> > > > > * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Don't > > allow wv/wu constraints to be ALTIVEC_REGISTERS unless DF/SF can > > occupy the Altivec registers. > > Okay. > > Can you add a testcase to catch this in the future? You only see it in big programs with agressive optimizations. I did not see it during the normal testing (bootstrap, etc.). The failure is reload complaining it can't find an Altivec register to spill if the move pattern has an option for only Altivec registers. It isn't like bad code is silently generated. I will check the 5 spec benchmarks that failed with to see if I can extract one module that shows it off.
On Thu, Sep 26, 2013 at 06:56:37PM -0400, David Edelsohn wrote: > On Thu, Sep 26, 2013 at 4:51 PM, Michael Meissner > <meissner@linux.vnet.ibm.com> wrote: > > I discovered that I was setting the wv/wu constraints incorrectly to > > ALTIVEC_REGS, which leads to reload failures in some cases. > > > > Is this patch ok to apply along with the previous patch assuming it bootstraps > > and has no regressions with make check? It builds the programs that had > > failures with the previous patch. > > > > 2013-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> > > > > * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Don't > > allow wv/wu constraints to be ALTIVEC_REGISTERS unless DF/SF can > > occupy the Altivec registers. > > Okay. > > Can you add a testcase to catch this in the future? I looked into this, and of the 5 spec benchmarks that did not compile without the fix, 4 are in fortran, and the 5th in C++ did not show up the error if I deleted any code, so there is no simple test case I know of.
Index: gcc/config/rs6000/rs6000-builtin.def =================================================================== --- gcc/config/rs6000/rs6000-builtin.def (revision 202846) +++ gcc/config/rs6000/rs6000-builtin.def (working copy) @@ -1209,9 +1209,9 @@ BU_VSX_1 (XVRSPIZ, "xvrspiz", CONS BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi) BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic) -BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, vsx_floordf2) -BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, vsx_ceildf2) -BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, vsx_btruncdf2) +BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, floordf2) +BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, ceildf2) +BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, btruncdf2) /* VSX predicate functions. */ BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p) Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 202874) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -2394,13 +2394,17 @@ rs6000_init_hard_regno_mode_ok (bool glo rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; if (TARGET_VSX_TIMODE) rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_ws] - = (TARGET_UPPER_REGS_DF) ? VSX_REGS : FLOAT_REGS; + if (TARGET_UPPER_REGS_DF) + { + rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; + } + else + rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS; } /* Add conditional constraints based on various options, to allow us to @@ -2420,12 +2424,16 @@ rs6000_init_hard_regno_mode_ok (bool glo if (TARGET_POWERPC64) rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; - if (TARGET_P8_VECTOR) + if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) { rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wy] - = rs6000_constraints[RS6000_CONSTRAINT_ww] - = (TARGET_UPPER_REGS_SF) ? VSX_REGS : FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS; + } + else if (TARGET_P8_VECTOR) + { + rs6000_constraints[RS6000_CONSTRAINT_wy] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; } else if (TARGET_VSX) rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 202846) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -617,6 +617,25 @@ extern int rs6000_vector_align[]; || rs6000_cpu == PROCESSOR_PPC8548) +/* Whether SF/DF operations are supported on the E500. */ +#define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \ + && !TARGET_FPRS) + +#define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ + && !TARGET_FPRS && TARGET_E500_DOUBLE) + +/* Whether SF/DF operations are supported by by the normal floating point unit + (or the vector/scalar unit). */ +#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ + && TARGET_SINGLE_FLOAT) + +#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ + && TARGET_DOUBLE_FLOAT) + +/* Whether SF/DF operations are supported by any hardware. */ +#define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE) +#define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE) + /* Which machine supports the various reciprocal estimate instructions. */ #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && TARGET_FPRS && TARGET_SINGLE_FLOAT)