From patchwork Thu May 28 19:26:40 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Snyder X-Patchwork-Id: 27800 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 17B8AB7081 for ; Fri, 29 May 2009 05:27:23 +1000 (EST) Received: by ozlabs.org (Postfix) id 33676DE29E; Fri, 29 May 2009 05:27:03 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 31E82DE29C for ; Fri, 29 May 2009 05:27:03 +1000 (EST) X-Original-To: linuxppc-dev@ozlabs.org Delivered-To: linuxppc-dev@ozlabs.org Received: from ovro.ovro.caltech.edu (ovro.ovro.caltech.edu [192.100.16.2]) by ozlabs.org (Postfix) with ESMTP id C6ECCDDFCC for ; Fri, 29 May 2009 05:26:43 +1000 (EST) Received: from ovro.caltech.edu (desk1.correlator.pvt [192.168.17.65]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ovro.ovro.caltech.edu (Postfix) with ESMTP id 238D99F8002; Thu, 28 May 2009 12:26:42 -0700 (PDT) Date: Thu, 28 May 2009 12:26:40 -0700 From: Ira Snyder To: linuxppc-dev@ozlabs.org, Li Yang , Dan Williams Subject: [PATCH] fsldma: do not clear bandwidth control bits on the 83xx controller Message-ID: <20090528192640.GC25993@ovro.caltech.edu> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.17+20080114 (2008-01-14) X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.0 (ovro.ovro.caltech.edu); Thu, 28 May 2009 12:26:42 -0700 (PDT) X-BeenThere: linuxppc-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org The 83xx controller does not support the external pause feature. The bit in the mode register that controls external pause on the 85xx controller happens to be part of the bandwidth control settings for the 83xx controller. This patch fixes the driver so that it only clears the external pause bit if the hardware is the 85xx controller. When driving the 83xx controller, the bit is left untouched. This follows the existing convention that mode registers settings are not touched unless necessary. Signed-off-by: Ira W. Snyder --- There is currently no interface to change the bandwidth control setting. I have changed the bandwidth control setting by requesting exclusive access to the DMA channel (via dma_request_channel()) then, since I know the channel is idle, I just add the value I need. I have tested this using the DMA_SLAVE patch I posted last week, and verified that the bandwidth control bits do not change on the 83xx controller. The conditional could be changed from "== 85XX" to "!= 83XX", as they are equivalent in the current driver. I'm not sure which is better. drivers/dma/fsldma.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index b2fd35e..a662aac 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -148,10 +148,11 @@ static void dma_start(struct fsl_dma_chan *fsl_chan) if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); mr_set |= FSL_DMA_MR_EMP_EN; - } else + } else if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~FSL_DMA_MR_EMP_EN, 32); + } if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT) mr_set |= FSL_DMA_MR_EMS_EN;