From patchwork Wed Sep 25 18:59:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 277962 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3EEF92C00CE for ; Thu, 26 Sep 2013 05:03:08 +1000 (EST) Received: from localhost ([::1]:54354 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOuMc-00031r-42 for incoming@patchwork.ozlabs.org; Wed, 25 Sep 2013 15:03:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35414) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOuJp-0000io-4y for qemu-devel@nongnu.org; Wed, 25 Sep 2013 15:00:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VOuJh-0008VV-1W for qemu-devel@nongnu.org; Wed, 25 Sep 2013 15:00:13 -0400 Received: from ssl.serverraum.org ([2a01:4f8:a0:1283::1:2]:46029) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOuJg-0008Oh-Gi for qemu-devel@nongnu.org; Wed, 25 Sep 2013 15:00:04 -0400 Received: from localhost (localhost [127.0.0.1]) by ssl.serverraum.org (Postfix) with ESMTP id 033863F099; Wed, 25 Sep 2013 21:00:04 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at ssl.serverraum.org Received: from ssl.serverraum.org ([127.0.0.1]) by localhost (ssl.serverraum.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2ergyKVvx0Al; Wed, 25 Sep 2013 21:00:03 +0200 (CEST) Received: from thanatos.fritz.box (88-134-163-112-dynip.superkabel.de [88.134.163.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id AE81F3F079; Wed, 25 Sep 2013 21:00:03 +0200 (CEST) From: Michael Walle To: qemu-devel@nongnu.org Date: Wed, 25 Sep 2013 20:59:30 +0200 Message-Id: <1380135572-25095-10-git-send-email-michael@walle.cc> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1380135572-25095-1-git-send-email-michael@walle.cc> References: <1380135572-25095-1-git-send-email-michael@walle.cc> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a01:4f8:a0:1283::1:2 Cc: Michael Walle Subject: [Qemu-devel] [PULL 09/11] target-lm32: add breakpoint/watchpoint support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds in-target breakpoint and watchpoint support. Signed-off-by: Michael Walle --- target-lm32/TODO | 2 -- target-lm32/cpu.c | 1 + target-lm32/cpu.h | 27 ++++++++++++-- target-lm32/helper.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++ target-lm32/helper.h | 3 ++ target-lm32/op_helper.c | 58 +++++++++++++++++++++++++++++- target-lm32/translate.c | 6 ++-- 7 files changed, 178 insertions(+), 8 deletions(-) diff --git a/target-lm32/TODO b/target-lm32/TODO index b9ea0c8..e163c42 100644 --- a/target-lm32/TODO +++ b/target-lm32/TODO @@ -1,3 +1 @@ -* disassembler (lm32-dis.c) * linux-user emulation -* native bp/wp emulation (?) diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 869878c..2ca8dee 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -71,6 +71,7 @@ static void lm32_cpu_initfn(Object *obj) if (tcg_enabled() && !tcg_initialized) { tcg_initialized = true; lm32_translate_init(); + cpu_set_debug_excp_handler(lm32_debug_excp_handler); } } diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index 67a785e..cef9167 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -172,8 +172,11 @@ struct CPULM32State { /* debug registers */ uint32_t dc; /* debug control */ - uint32_t bp[4]; /* breakpoint addresses */ - uint32_t wp[4]; /* watchpoint addresses */ + uint32_t bp[4]; /* breakpoints */ + uint32_t wp[4]; /* watchpoints */ + + CPUBreakpoint * cpu_breakpoint[4]; + CPUWatchpoint * cpu_watchpoint[4]; CPU_COMMON @@ -190,6 +193,19 @@ struct CPULM32State { }; +typedef enum { + LM32_WP_DISABLED = 0, + LM32_WP_READ, + LM32_WP_WRITE, + LM32_WP_READ_WRITE, +} lm32_wp_t; + +static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx) +{ + assert(idx < 4); + return (dc >> (idx+1)*2) & 0x3; +} + #include "cpu-qom.h" LM32CPU *cpu_lm32_init(const char *cpu_model); @@ -202,6 +218,13 @@ int cpu_lm32_signal_handler(int host_signum, void *pinfo, void *puc); void lm32_translate_init(void); void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value); +void QEMU_NORETURN raise_exception(CPULM32State *env, int index); +void lm32_debug_excp_handler(CPULM32State *env); +void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address); +void lm32_breakpoint_remove(CPULM32State *env, int index); +void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address, + lm32_wp_t wp_type); +void lm32_watchpoint_remove(CPULM32State *env, int index); static inline CPULM32State *cpu_init(const char *cpu_model) { diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 383bcf3..cff1b95 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -49,6 +49,95 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } } +void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address) +{ + cpu_breakpoint_insert(env, address, BP_CPU, &env->cpu_breakpoint[idx]); +} + +void lm32_breakpoint_remove(CPULM32State *env, int idx) +{ + if (!env->cpu_breakpoint[idx]) { + return; + } + + cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[idx]); + env->cpu_breakpoint[idx] = NULL; +} + +void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, + lm32_wp_t wp_type) +{ + int flags = 0; + + switch (wp_type) { + case LM32_WP_DISABLED: + /* nothing to to */ + break; + case LM32_WP_READ: + flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ; + break; + case LM32_WP_WRITE: + flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE; + break; + case LM32_WP_READ_WRITE: + flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS; + break; + } + + if (flags != 0) { + cpu_watchpoint_insert(env, address, 1, flags, + &env->cpu_watchpoint[idx]); + } +} + +void lm32_watchpoint_remove(CPULM32State *env, int idx) +{ + if (!env->cpu_watchpoint[idx]) { + return; + } + + cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[idx]); + env->cpu_watchpoint[idx] = NULL; +} + +static bool check_watchpoints(CPULM32State *env) +{ + LM32CPU *cpu = lm32_env_get_cpu(env); + int i; + + for (i = 0; i < cpu->def->num_watchpoints; i++) { + if (env->cpu_watchpoint[i] && + env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) { + return true; + } + } + return false; +} + +void lm32_debug_excp_handler(CPULM32State *env) +{ + CPUBreakpoint *bp; + + if (env->watchpoint_hit) { + if (env->watchpoint_hit->flags & BP_CPU) { + env->watchpoint_hit = NULL; + if (check_watchpoints(env)) { + raise_exception(env, EXCP_WATCHPOINT); + } else { + cpu_resume_from_signal(env, NULL); + } + } + } else { + QTAILQ_FOREACH(bp, &env->breakpoints, entry) + if (bp->pc == env->pc) { + if (bp->flags & BP_CPU) { + raise_exception(env, EXCP_BREAKPOINT); + } + break; + } + } +} + void lm32_cpu_do_interrupt(CPUState *cs) { LM32CPU *cpu = LM32_CPU(cs); diff --git a/target-lm32/helper.h b/target-lm32/helper.h index 3ea15a6..ad44fdf 100644 --- a/target-lm32/helper.h +++ b/target-lm32/helper.h @@ -2,6 +2,9 @@ DEF_HELPER_2(raise_exception, void, env, i32) DEF_HELPER_1(hlt, void, env) +DEF_HELPER_3(wcsr_bp, void, env, i32, i32) +DEF_HELPER_3(wcsr_wp, void, env, i32, i32) +DEF_HELPER_2(wcsr_dc, void, env, i32) DEF_HELPER_2(wcsr_im, void, env, i32) DEF_HELPER_2(wcsr_ip, void, env, i32) DEF_HELPER_2(wcsr_jtx, void, env, i32) diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index 8f5ef55..71f21d1 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -19,12 +19,17 @@ #define SHIFT 3 #include "exec/softmmu_template.h" -void HELPER(raise_exception)(CPULM32State *env, uint32_t index) +void raise_exception(CPULM32State *env, int index) { env->exception_index = index; cpu_loop_exit(env); } +void HELPER(raise_exception)(CPULM32State *env, uint32_t index) +{ + raise_exception(env, index); +} + void HELPER(hlt)(CPULM32State *env) { CPUState *cs = CPU(lm32_env_get_cpu(env)); @@ -34,6 +39,57 @@ void HELPER(hlt)(CPULM32State *env) cpu_loop_exit(env); } +void HELPER(wcsr_bp)(CPULM32State *env, uint32_t bp, uint32_t idx) +{ + uint32_t addr = bp & ~1; + + assert(idx < 4); + + env->bp[idx] = bp; + lm32_breakpoint_remove(env, idx); + if (bp & 1) { + lm32_breakpoint_insert(env, idx, addr); + } +} + +void HELPER(wcsr_wp)(CPULM32State *env, uint32_t wp, uint32_t idx) +{ + lm32_wp_t wp_type; + + assert(idx < 4); + + env->wp[idx] = wp; + + wp_type = lm32_wp_type(env->dc, idx); + lm32_watchpoint_remove(env, idx); + if (wp_type != LM32_WP_DISABLED) { + lm32_watchpoint_insert(env, idx, wp, wp_type); + } +} + +void HELPER(wcsr_dc)(CPULM32State *env, uint32_t dc) +{ + uint32_t old_dc; + int i; + lm32_wp_t old_type; + lm32_wp_t new_type; + + old_dc = env->dc; + env->dc = dc; + + for (i = 0; i < 4; i++) { + old_type = lm32_wp_type(old_dc, i); + new_type = lm32_wp_type(dc, i); + + if (old_type != new_type) { + lm32_watchpoint_remove(env, i); + if (new_type != LM32_WP_DISABLED) { + lm32_watchpoint_insert(env, i, env->wp[i], new_type); + } + } + } +} + void HELPER(wcsr_im)(CPULM32State *env, uint32_t im) { lm32_pic_set_im(env->pic_state, im); diff --git a/target-lm32/translate.c b/target-lm32/translate.c index c8c862e..5abd2aa 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -873,7 +873,7 @@ static void dec_wcsr(DisasContext *dc) gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]); break; case CSR_DC: - tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]); + gen_helper_wcsr_dc(cpu_env, cpu_R[dc->r1]); break; case CSR_BP0: case CSR_BP1: @@ -885,7 +885,7 @@ static void dec_wcsr(DisasContext *dc) "breakpoint #%i is not available\n", no); break; } - tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]); + gen_helper_wcsr_bp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no)); break; case CSR_WP0: case CSR_WP1: @@ -897,7 +897,7 @@ static void dec_wcsr(DisasContext *dc) "watchpoint #%i is not available\n", no); break; } - tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]); + gen_helper_wcsr_wp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no)); break; case CSR_CC: case CSR_CFG: