From patchwork Wed Sep 25 16:27:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 277927 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4A3F72C00BD for ; Thu, 26 Sep 2013 02:47:22 +1000 (EST) Received: from localhost ([::1]:53877 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOs4P-0005a7-QJ for incoming@patchwork.ozlabs.org; Wed, 25 Sep 2013 12:36:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57740) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOrwi-0002hy-Nb for qemu-devel@nongnu.org; Wed, 25 Sep 2013 12:28:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VOrwc-000382-Tp for qemu-devel@nongnu.org; Wed, 25 Sep 2013 12:28:12 -0400 Received: from mail-pd0-x22b.google.com ([2607:f8b0:400e:c02::22b]:34638) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOrwc-00037w-J5 for qemu-devel@nongnu.org; Wed, 25 Sep 2013 12:28:06 -0400 Received: by mail-pd0-f171.google.com with SMTP id g10so6277002pdj.30 for ; Wed, 25 Sep 2013 09:28:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=uOlKr9S4sA3w1zFsnsSkJv4SoBRWmGBFfODUomBluA8=; b=PF8NOK9B0L6xHh22dKSA6WLAjQvRb9TBlcsYYtsIYYeBhhmqCCnNU8B7MlOsioAyUf wpqsp7U04m7LIWn+9S6NUH/ME+5fJTB0MPkj12yMrV57y8QiFkDShGnAqPJBdlrUD+D0 1dxVriscUsZRv1LIKwy4w8N4PB11dnYSpfgO6d0Ck0rMISAZLcKDQ65NSBvvemLoWNXb w/+dnO9JCPrDlQldzdYkcRFloqqGGtJKHn5la/fMHgAzvO23YxhLEdAd5ZQ1Ym2zvuPH +u4q1p0bM7GpNHyIk+nbnL4Bwaoqyvoq6bk1dLtj4+voCiCzZlrBS+qs+WTa3nGIohb1 1nRQ== X-Received: by 10.68.179.65 with SMTP id de1mr24264339pbc.73.1380126485701; Wed, 25 Sep 2013 09:28:05 -0700 (PDT) Received: from anchor.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id oj6sm54530947pab.9.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 25 Sep 2013 09:28:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 25 Sep 2013 09:27:33 -0700 Message-Id: <1380126458-3247-17-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1380126458-3247-1-git-send-email-rth@twiddle.net> References: <1380126458-3247-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::22b Cc: anthony@codemonkey.ws Subject: [Qemu-devel] [PULL 16/21] tcg-ppc64: Tidy register allocation order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Remove conditionalization from tcg_target_reg_alloc_order, relying on reserved_regs to prevent register allocation that shouldn't happen. So R11 is now present in reg_alloc_order for __APPLE__, but also now reserved. Sort reg_alloc_order into call-saved, call-clobbered, and parameters. This reduces the effect of values getting spilled and reloaded before function calls. Whether or not it is reserved, R2 (TOC) is always call-clobbered. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 49 ++++++++++++++++++++++--------------------------- 1 file changed, 22 insertions(+), 27 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 0659dd6..c01a8bb 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -99,7 +99,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #endif static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R14, + TCG_REG_R14, /* call saved registers */ TCG_REG_R15, TCG_REG_R16, TCG_REG_R17, @@ -109,29 +109,25 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R21, TCG_REG_R22, TCG_REG_R23, + TCG_REG_R24, + TCG_REG_R25, + TCG_REG_R26, + TCG_REG_R27, TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31, -#ifdef __APPLE__ + TCG_REG_R12, /* call clobbered, non-arguments */ + TCG_REG_R11, TCG_REG_R2, -#endif - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, + TCG_REG_R10, /* call clobbered, arguments */ TCG_REG_R9, - TCG_REG_R10, -#ifndef __APPLE__ - TCG_REG_R11, -#endif - TCG_REG_R12, - TCG_REG_R24, - TCG_REG_R25, - TCG_REG_R26, - TCG_REG_R27 + TCG_REG_R8, + TCG_REG_R7, + TCG_REG_R6, + TCG_REG_R5, + TCG_REG_R4, + TCG_REG_R3, }; static const int tcg_target_call_iarg_regs[] = { @@ -2133,9 +2129,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); tcg_regset_set32(tcg_target_call_clobber_regs, 0, (1 << TCG_REG_R0) | -#ifdef __APPLE__ (1 << TCG_REG_R2) | -#endif (1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | @@ -2145,16 +2139,17 @@ static void tcg_target_init(TCGContext *s) (1 << TCG_REG_R9) | (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | - (1 << TCG_REG_R12) - ); + (1 << TCG_REG_R12)); tcg_regset_clear(s->reserved_regs); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); -#ifndef __APPLE__ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ +#ifdef __APPLE__ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R11); /* ??? */ +#else + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc */ #endif - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ tcg_add_target_add_op_defs(ppc_op_defs); }