From patchwork Wed Sep 25 13:34:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Brodkin X-Patchwork-Id: 277863 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AF7182C0332 for ; Wed, 25 Sep 2013 23:40:47 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 67BDD4A07F; Wed, 25 Sep 2013 15:40:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8+TiJE5ZCsET; Wed, 25 Sep 2013 15:40:44 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 622CC4A080; Wed, 25 Sep 2013 15:40:40 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 869F64A081 for ; Wed, 25 Sep 2013 15:40:32 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id H5ZcVLWV+6Oy for ; Wed, 25 Sep 2013 15:40:25 +0200 (CEST) X-Greylist: delayed 374 seconds by postgrey-1.27 at theia; Wed, 25 Sep 2013 15:40:17 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from vaxjo.synopsys.com (us02smtp1.synopsys.com [198.182.60.75]) by theia.denx.de (Postfix) with ESMTP id 55F3D4A07F for ; Wed, 25 Sep 2013 15:40:17 +0200 (CEST) Received: from WBSNus02mta2 (us02secmta2.synopsys.com [10.12.235.98]) by vaxjo.synopsys.com (Postfix) with ESMTP id 096D1DA75; Wed, 25 Sep 2013 06:34:09 -0700 (PDT) Received: from us02secmta2.internal.synopsys.com (us02secmta2.internal.synopsys.com [127.0.0.1]) by us02secmta2.internal.synopsys.com (Service) with ESMTP id ED1DD55F13; Wed, 25 Sep 2013 06:34:08 -0700 (PDT) Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by us02secmta2.internal.synopsys.com (Service) with ESMTP id A3D8955F02; Wed, 25 Sep 2013 06:34:08 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 9193D749; Wed, 25 Sep 2013 06:34:08 -0700 (PDT) Received: from US01WXQAHTC1.internal.synopsys.com (us01wxqahtc1.internal.synopsys.com [10.12.238.230]) by mailhost.synopsys.com (Postfix) with ESMTP id 883F6748; Wed, 25 Sep 2013 06:34:08 -0700 (PDT) Received: from DE02WEHTCA.internal.synopsys.com (10.225.19.27) by US01WXQAHTC1.internal.synopsys.com (10.12.238.230) with Microsoft SMTP Server (TLS) id 14.2.298.4; Wed, 25 Sep 2013 06:34:08 -0700 Received: from abrodkin-8560l.internal.synopsys.com (10.121.8.99) by DE02WEHTCA.internal.synopsys.com (10.225.19.80) with Microsoft SMTP Server (TLS) id 14.2.298.4; Wed, 25 Sep 2013 15:34:07 +0200 From: Alexey Brodkin To: Date: Wed, 25 Sep 2013 17:34:01 +0400 Message-ID: <1380116041-24750-1-git-send-email-abrodkin@synopsys.com> X-Mailer: git-send-email 1.8.1.2 MIME-Version: 1.0 X-Originating-IP: [10.121.8.99] Cc: sr@denx.de, Mischa.Jonker@synopsys.com, Alexey Brodkin Subject: [U-Boot] [PATCH] drivers/net/designware - fix alignment of buffer descriptors X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de It's important that buffer descriptors are aligned in accordance to GMAC data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes) for every bus width type. If buffer descriptor is improperly aligned GMAC discards lower bits of provided address and as a result reads from improper location that doesn't match expected fields. Any other members of structure "dw_eth_dev" (and structure itself) don't need any specific alignment. Moreover commit ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple updates/enhancements to designware.c" introduced another structure member "link_printed" right before buffer descriptors while "padding" member was left untouched. This together with alignment of structure itself to 8-byte boundary forces buffer descriptoprs always to be 4-byte aligned that causes driver complete disfunction if GMAC bus width is 64 or 128-bit. Proposed change makes sure all buffer descriptors are 128-bit aligned. Signed-off-by: Alexey Brodkin --- drivers/net/designware.c | 6 +----- drivers/net/designware.h | 7 +++---- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index f11cb0b..c8e3fc8 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -534,11 +534,7 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) if (!dev) return -ENOMEM; - /* - * Since the priv structure contains the descriptors which need a strict - * buswidth alignment, memalign is used to allocate memory - */ - priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + priv = (struct dw_eth_dev *) malloc(sizeof(struct dw_eth_dev)); if (!priv) { free(dev); return -ENOMEM; diff --git a/drivers/net/designware.h b/drivers/net/designware.h index d668f8f..137acb0 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -128,7 +128,7 @@ struct dmamacdescr { u32 dmamac_cntl; void *dmamac_addr; struct dmamacdescr *dmamac_next; -}; +} __aligned(16); /* * txrx_status definitions @@ -240,8 +240,7 @@ struct dw_eth_dev { u32 tx_currdescnum; u32 rx_currdescnum; u32 phy_configured; - int link_printed; - u32 padding; + u32 link_printed; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; @@ -253,7 +252,7 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; struct eth_device *dev; -} __attribute__ ((aligned(8))); +}; /* Speed specific definitions */ #define SPEED_10M 1