From patchwork Tue Sep 24 18:20:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagannadha Sutradharudu Teki X-Patchwork-Id: 277569 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 66AC72C00CE for ; Wed, 25 Sep 2013 04:33:04 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A6EAE4A11A; Tue, 24 Sep 2013 20:32:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Pg+hDDP44cY0; Tue, 24 Sep 2013 20:32:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 619C84A0B6; Tue, 24 Sep 2013 20:31:15 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 85E954A09D for ; Tue, 24 Sep 2013 20:31:05 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ScWkiPKehnEd for ; Tue, 24 Sep 2013 20:31:01 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from tx2outboundpool.messaging.microsoft.com (tx2ehsobe003.messaging.microsoft.com [65.55.88.13]) by theia.denx.de (Postfix) with ESMTPS id 5CD584A067 for ; Tue, 24 Sep 2013 20:30:43 +0200 (CEST) Received: from mail164-tx2-R.bigfish.com (10.9.14.228) by TX2EHSOBE011.bigfish.com (10.9.40.31) with Microsoft SMTP Server id 14.1.225.22; Tue, 24 Sep 2013 18:30:41 +0000 Received: from mail164-tx2 (localhost [127.0.0.1]) by mail164-tx2-R.bigfish.com (Postfix) with ESMTP id A0BE26008C; Tue, 24 Sep 2013 18:30:41 +0000 (UTC) X-Forefront-Antispam-Report: CIP:149.199.60.83; KIP:(null); UIP:(null); IPV:NLI; H:xsj-gw1; RD:unknown-60-83.xilinx.com; EFVD:NLI X-SpamScore: 1 X-BigFish: VPS1(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bhz2fh95h839hd24hf0ah119dh1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h906i1155h192ch) Received-SPF: pass (mail164-tx2: domain of xilinx.com designates 149.199.60.83 as permitted sender) client-ip=149.199.60.83; envelope-from=jagannadha.sutradharudu-teki@xilinx.com; helo=xsj-gw1 ; helo=xsj-gw1 ; Received: from mail164-tx2 (localhost.localdomain [127.0.0.1]) by mail164-tx2 (MessageSwitch) id 1380047438964805_18086; Tue, 24 Sep 2013 18:30:38 +0000 (UTC) Received: from TX2EHSMHS040.bigfish.com (unknown [10.9.14.243]) by mail164-tx2.bigfish.com (Postfix) with ESMTP id DBECC260062; Tue, 24 Sep 2013 18:30:38 +0000 (UTC) Received: from xsj-gw1 (149.199.60.83) by TX2EHSMHS040.bigfish.com (10.9.99.140) with Microsoft SMTP Server id 14.16.227.3; Tue, 24 Sep 2013 18:30:38 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-smtp1.xilinx.com) by xsj-gw1 with esmtp (Exim 4.63) (envelope-from ) id 1VOXNe-0003Vf-Ca; Tue, 24 Sep 2013 11:30:38 -0700 From: Jagannadha Sutradharudu Teki To: Date: Tue, 24 Sep 2013 23:50:11 +0530 X-Mailer: git-send-email 1.8.3 In-Reply-To: <1380046813-12174-1-git-send-email-jaganna@xilinx.com> References: <1380046813-12174-1-git-send-email-jaganna@xilinx.com> X-RCIS-Action: ALLOW MIME-Version: 1.0 Message-ID: <83b1f844-3b11-4e77-803a-7f6d086803d3@TX2EHSMHS040.ehs.local> X-OriginatorOrg: xilinx.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: Willis Max , Jagannadha Sutradharudu Teki , Syed Hussain , "Todd Legler \(tlegler\)" , Tom Rini , Sascha Silbe Subject: [U-Boot] [PATCH v4 34/36] sf: Set quad enable bit support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch provides support to set the quad enable bit on flash. quad enable bit needs to set before performing any quad IO operations on respective SPI flashes. Signed-off-by: Jagannadha Sutradharudu Teki --- Changes for v4: - none Changes for v3: - none Changes for v2: - none drivers/mtd/spi/spi_flash_internal.h | 5 +++++ drivers/mtd/spi/spi_flash_ops.c | 24 ++++++++++++++++++++++++ drivers/mtd/spi/spi_flash_probe.c | 9 +++++++++ 3 files changed, 38 insertions(+) diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 1f9f170..a346ae6 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -22,6 +22,7 @@ #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 +#define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 #define CMD_WRITE_ENABLE 0x06 #define CMD_ERASE_4K 0x20 @@ -41,6 +42,7 @@ /* Common status */ #define STATUS_WIP 0x01 +#define STATUS_QEB 0x02 #define STATUS_PEC 0x80 /* Send a single-byte command to the device and read the response */ @@ -94,6 +96,9 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) /* Program the status register. */ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr); +/* Set quad enbale bit */ +int spi_flash_set_qeb(struct spi_flash *flash); + /* * Same as spi_flash_cmd_read() except it also claims/releases the SPI * bus. Used as common part of the ->read() operation. diff --git a/drivers/mtd/spi/spi_flash_ops.c b/drivers/mtd/spi/spi_flash_ops.c index 2f87801..439490e 100644 --- a/drivers/mtd/spi/spi_flash_ops.c +++ b/drivers/mtd/spi/spi_flash_ops.c @@ -62,6 +62,30 @@ static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr) return 0; } +int spi_flash_set_qeb(struct spi_flash *flash) +{ + u8 qeb_status; + u8 cmd; + int ret; + + cmd = CMD_READ_CONFIG; + ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1); + if (ret < 0) { + debug("SF: fail to read config register\n"); + return ret; + } + + if (qeb_status & STATUS_QEB) { + debug("SF: Quad enable bit is already set\n"); + } else { + ret = spi_flash_cmd_write_config(flash, STATUS_QEB); + if (ret < 0) + return ret; + } + + return ret; +} + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { diff --git a/drivers/mtd/spi/spi_flash_probe.c b/drivers/mtd/spi/spi_flash_probe.c index 30ef85c..995af14 100644 --- a/drivers/mtd/spi/spi_flash_probe.c +++ b/drivers/mtd/spi/spi_flash_probe.c @@ -237,6 +237,15 @@ struct spi_flash *spi_flash_validate_ids(struct spi_slave *spi, u8 *idcode) flash->write_cmd = flash->spi->wr_cmd; } + /* Set the quad enable bit - only for quad commands */ + if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || + (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { + if (spi_flash_set_qeb(flash)) { + debug("SF: Fail to set quad enable bit\n"); + return NULL; + } + } + /* Compute erase sector and command */ if (params->flags & SECT_4K) { flash->erase_cmd = CMD_ERASE_4K;