Patchwork [U-Boot,v2] boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLD

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Submitter Prabhakar Kushwaha
Date Sept. 24, 2013, 10:28 a.m.
Message ID <1380018515-14875-1-git-send-email-prabhakar@freescale.com>
Download mbox | patch
Permalink /patch/277426/
State Accepted
Delegated to: York Sun
Headers show

Comments

Prabhakar Kushwaha - Sept. 24, 2013, 10:28 a.m.
NAND,CPLD AMASK register is programmed for 64K size.

so Update TLB & LAW size accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---

 Based upon git://git.denx.de/u-boot.git branch master

  changes for v2: 
  - Updated both CPLD and NAND

 board/freescale/c29xpcie/law.c |    4 ++--
 board/freescale/c29xpcie/tlb.c |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)
York Sun - Oct. 1, 2013, 3:51 p.m.
On 09/24/2013 03:28 AM, Prabhakar Kushwaha wrote:
>  NAND,CPLD AMASK register is programmed for 64K size.
> 
> so Update TLB & LAW size accordingly.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> 
>  Based upon git://git.denx.de/u-boot.git branch master
> 
>   changes for v2: 
>   - Updated both CPLD and NAND
> 

Applied to u-boot-mpc85xx/next branch, pending merging to
u-boot-mpc85xx/master branch.

York

Patch

diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c
index cd8fc21..80e5fff 100644
--- a/board/freescale/c29xpcie/law.c
+++ b/board/freescale/c29xpcie/law.c
@@ -10,8 +10,8 @@ 
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
 					LAW_TRGT_IF_PLATFORM_SRAM),
 };
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index ddd1ef8..84844ee 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -46,11 +46,11 @@  struct fsl_e_tlb_entry tlb_table[] = {
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 4, BOOKE_PAGESZ_4K, 1),
+			0, 4, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 5, BOOKE_PAGESZ_16K, 1),
+			0, 5, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
 			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,