From patchwork Thu Sep 19 16:01:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 275993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 43D112C010F for ; Fri, 20 Sep 2013 02:05:24 +1000 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VMgiD-0004Hq-Kg; Thu, 19 Sep 2013 16:04:14 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VMghn-0001Hv-EN; Thu, 19 Sep 2013 16:03:47 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VMgh2-00015i-Qm for linux-mtd@lists.infradead.org; Thu, 19 Sep 2013 16:03:07 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id D76D610C5; Thu, 19 Sep 2013 18:02:56 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.3.2 Received: from localhost.localdomain (unknown [190.2.109.158]) by mail.free-electrons.com (Postfix) with ESMTPA id 7994A8BD; Thu, 19 Sep 2013 18:02:53 +0200 (CEST) From: Ezequiel Garcia To: Subject: [PATCH 18/21] ARM: mvebu: Add a fixed 0Hz clock to represent NAND clock Date: Thu, 19 Sep 2013 13:01:42 -0300 Message-Id: <1379606505-2529-19-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1379606505-2529-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1379606505-2529-1-git-send-email-ezequiel.garcia@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130919_120301_337584_F624B3D5 X-CRM114-Status: GOOD ( 10.05 ) X-Spam-Score: 1.7 (+) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (1.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- 3.6 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -0.6 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Thomas Petazzoni , Lior Amsalem , Jason Cooper , Tawfik Bayouk , Artem Bityutskiy , Daniel Mack , Ezequiel Garcia , Gregory Clement , Brian Norris , Willy Tarreau X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The NAND controller in Armada 370 and Armada XP SoC has an input clock that's either 125 MHz or 200 MHz. As a temporary representation, this commit adds a 0Hz fixed-clock compatible DT node. Not-Signed-off-by: Ezequiel Garcia --- Of course, this is not intended for inclusion and I'm adding it to the series only to allow the driver's probe() to get the clock. This clock shouldn't be used anywhere, which means we must set "marvell,keep-config" parameter in the NAND device tree node. arch/arm/boot/dts/armada-370-xp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 90b1176..2e00da4 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -37,6 +37,15 @@ }; }; + clocks { + /* NAND reference clock */ + nandclk: nd_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>;