@@ -621,6 +621,24 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
return config;
}
+/*
+ * Get the DMA bus width field of the network configuration register that we
+ * should program. We find the width from decoding the design configuration
+ * register to find the maximum supported data bus width.
+ */
+static u32 macb_dbw(struct macb_device *macb)
+{
+ switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
+ case 4:
+ return GEM_BF(DBW, GEM_DBW128);
+ case 2:
+ return GEM_BF(DBW, GEM_DBW64);
+ case 1:
+ default:
+ return GEM_BF(DBW, GEM_DBW32);
+ }
+}
+
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
@@ -665,7 +683,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
*/
if (macb_is_gem(macb)) {
ncfgr = gem_mdc_clk_div(id, macb);
- ncfgr |= GEM_BF(DBW, 1);
+ ncfgr |= macb_dbw(macb);
} else {
ncfgr = macb_mdc_clk_div(id, macb);
}
@@ -58,6 +58,9 @@
#define MACB_WOL 0x00c4
#define MACB_MID 0x00fc
+/* GEM specific register offsets */
+#define GEM_DCFG1 0x0280
+
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
#define MACB_LB_SIZE 1
@@ -242,6 +245,14 @@
#define MACB_IDNUM_SIZE 16
/* Bitfields in DCFG1 */
+#define GEM_DBWDEF_OFFSET 25
+#define GEM_DBWDEF_SIZE 3
+
+/* constants for data bus width */
+#define GEM_DBW32 0
+#define GEM_DBW64 1
+#define GEM_DBW128 2
+
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
Get DMA bus width from design config register Signed-off-by: Bo Shen <voice.shen@atmel.com> --- drivers/net/macb.c | 20 +++++++++++++++++++- drivers/net/macb.h | 11 +++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-)