From patchwork Tue Sep 17 17:48:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elie De Brauwer X-Patchwork-Id: 275516 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 76FB32C00C9 for ; Wed, 18 Sep 2013 03:49:55 +1000 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VLzP7-0001Oz-1n; Tue, 17 Sep 2013 17:49:37 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VLzP5-0003pF-Dy; Tue, 17 Sep 2013 17:49:35 +0000 Received: from mail-ea0-x230.google.com ([2a00:1450:4013:c01::230]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VLzP2-0003or-Cu for linux-mtd@lists.infradead.org; Tue, 17 Sep 2013 17:49:34 +0000 Received: by mail-ea0-f176.google.com with SMTP id q16so2895425ead.21 for ; Tue, 17 Sep 2013 10:49:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FanafVYElw2RlE+xhI+vNO907NXMvZdt+nEHSHyWHZo=; b=anPOhRAD6JRihJTBXUGse676bVOjzLdTfOhED8Yi3wGnZ0mcv+wQkar2eKcHUft/V7 oVecrAjiCzqQ3/0ZNnzohrhDR3nSb2dqoyhTJR/vj7iZanaWFTTPajkLt4yGxsiCTaHw /FVbuzJQPZuHAsC+AMSf1bZ/PywJ0j9zq+Gm0sSJqoitAhmjA+g3pF2Pa3ghU41JyR3o 9Od1h3GK7hxK5IDZw4HBQ5G3BI2cedLXPd8K8Q2yUdxP1hcgN7CnhkwwB4QJyxkVArEN Fm4JY7T9qHtNrKjL+lSLmDHRL0h4RrH/JfPlVJl1H0waTmEbC+ylZro3bG913JTF6rrz tZLA== X-Received: by 10.14.206.201 with SMTP id l49mr2417281eeo.99.1379440148662; Tue, 17 Sep 2013 10:49:08 -0700 (PDT) Received: from lapelidb.telenet.be (dD576B3C8.access.telenet.be. [213.118.179.200]) by mx.google.com with ESMTPSA id d8sm52853423eeh.8.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 17 Sep 2013 10:49:07 -0700 (PDT) From: Elie De Brauwer To: computersforpeace@gmail.com Subject: [PATCH] mtd: m25p80: Fix 4 byte addressing mode for Micron devices. Date: Tue, 17 Sep 2013 19:48:22 +0200 Message-Id: <1379440103-5167-1-git-send-email-eliedebrauwer@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <20130917014706.GL4550@ld-irv-0074.broadcom.com> References: <20130917014706.GL4550@ld-irv-0074.broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130917_134932_619911_792A20E4 X-CRM114-Status: GOOD ( 11.42 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (eliedebrauwer[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Elie De Brauwer , linux-mtd@lists.infradead.org X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte addressing mode should be entered as follows: To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. (Note: The WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the command is immediate; after the command has been executed, the write enable latch bit is cleared to 0. Micron's portable way to perform this for all types of Micron flash is to first issue a write enable, then switch the addressing mode followed by a write disable to avoid leaving the flash in a write- able state. --- drivers/mtd/devices/m25p80.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 26b14f9..272d483 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -169,8 +169,16 @@ static inline int write_disable(struct m25p *flash) static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable) { switch (JEDEC_MFR(jedec_id)) { - case CFI_MFR_MACRONIX: case CFI_MFR_ST: /* Micron, actually */ + { + int status; + write_enable(flash); + flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B; + status = spi_write(flash->spi, flash->command, 1); + write_disable(flash); + return status; + } + case CFI_MFR_MACRONIX: case 0xEF /* winbond */: flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B; return spi_write(flash->spi, flash->command, 1);