Patchwork [U-Boot,04/10] arm: vf610: add anadig pll5 definitions

login
register
mail settings
Submitter Marcel Ziswiler
Date Sept. 17, 2013, 10:45 a.m.
Message ID <09098188dfdf3ba1a9a0cb6920efd318f295394a.1379414181.git.marcel@ziswiler.com>
Download mbox | patch
Permalink /patch/275430/
State Superseded
Delegated to: Albert ARIBAUD
Headers show

Comments

Marcel Ziswiler - Sept. 17, 2013, 10:45 a.m.
Add ANADIG PLL5 control definitions required for Ethernet RMII clock
configuration.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
---
 arch/arm/include/asm/arch-vf610/crm_regs.h |    4 ++++
 1 file changed, 4 insertions(+)

Patch

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 490e368..d4ad957 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -187,6 +187,10 @@  struct anadig_reg {
 #define CCM_CCGR9_FEC0_CTRL_MASK		0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
 
+#define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
+#define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)
+#define ANADIG_PLL5_CTRL_POWERDOWN              (1 << 12)
+#define ANADIG_PLL5_CTRL_DIV_SELECT		1
 #define ANADIG_PLL2_CTRL_ENABLE			(1 << 13)
 #define ANADIG_PLL2_CTRL_POWERDOWN		(1 << 12)
 #define ANADIG_PLL2_CTRL_DIV_SELECT		1